- branch page cross bug fixed.

diff --git a/simulation/cpu/alu.vhd b/simulation/cpu/alu.vhd
index 53caf50..5914357 100644 (file)
--- a/simulation/cpu/alu.vhd
+++ b/simulation/cpu/alu.vhd
@@ -789,10 +789,23 @@ begin
     elsif sel = ADDR_SIGNED_ADD then
         res := ('0' & addr1) + ('0' & addr2);
         addr_out <= res(dsize - 1 downto 0);
-        if ((addr2(dsize - 1) = '0' and res(dsize) = '1') or 
-        ---positive value add.
-            (addr2(dsize - 1) = '1' and addr1(dsize - 1 ) /= res(dsize - 1))) then
-        ---negative value add.
+--        if (addr2(dsize - 1) = '0') then
+--            ---positive value add.
+--            if (res(dsize) = '1') then
+--                carry_out <= '1';
+--            else
+--                carry_out <= '0';
+--            end if;
+--        else
+--            ---negative value add.
+--            if (res(dsize) = '0') then
+--                carry_out <= '1';
+--            else
+--                carry_out <= '0';
+--            end if;
+--        end if;
+        -->>>simplified above.
+        if ((addr2(dsize - 1) xor res(dsize)) = '1') then
             carry_out <= '1';
         else
             carry_out <= '0';

diff --git a/tools/test-image/sample1.asm b/tools/test-image/sample1.asm
index 8437ba2..873c805 100644 (file)
--- a/tools/test-image/sample1.asm
+++ b/tools/test-image/sample1.asm
@@ -608,6 +608,81 @@ boundary_3_4:
     stx $a4, y\r
     sty $a4, x\r
 \r
+    ;;branch page cross test.\r
+    jmp bl_test0\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+bl_test0:\r
+    ldx #5\r
+bl_test1:\r
+    dex\r
+    ;;forward branch\r
+    bpl bl_test2\r
+\r
+    jmp bl_test2\r
+    .byte $00, $01, $02, $03, $04, $05, $06, $07, $08, $09, $0a, $0b, $0c, $0d, $0e, $0f\r
+    .byte $00, $01, $02, $03, $04, $05, $06, $07, $08, $09, $0a, $0b, $0c, $0d, $0e, $0f\r
+    .byte $00, $01, $02, $03, $04, $05, $06, $07, $08, $09, $0a, $0b, $0c, $0d, $0e, $0f\r
+    .byte $00, $01, $02, $03, $04, $05, $06, $07, $08, $09, $0a, $0b, $0c, $0d, $0e, $0f\r
+    .byte $00, $01, $02, $03, $04, $05, $06, $07, $08, $09, $0a, $0b, $0c, $0d, $0e, $0f\r
+    .byte $00, $01, $02, $03, $04, $05, $06, $07, $08, $09, $0a, $0b, $0c, $0d, $0e, $0f\r
+    .byte $00, $01, $02, $03, $04, $05, $06, $07, $08, $09, $0a, $0b, $0c, $0d, $0e, $0f\r
+\r
+bl_test2:\r
+    dex\r
+    ;;backward branch\r
+    bpl bl_test1\r
+\r
+    ;;test2\r
+    ldx #5\r
+bl_test3:\r
+    dex\r
+    bpl bl_test4\r
+\r
+    jmp bl_test4\r
+\r
+    .byte $00, $01, $02, $03, $04, $05, $06, $07, $08, $09, $0a, $0b, $0c, $0d, $0e, $0f\r
+    .byte $00, $01, $02, $03, $04, $05, $06, $07, $08, $09, $0a, $0b, $0c, $0d, $0e, $0f\r
+    .byte $00, $01, $02, $03, $04, $05, $06, $07, $08, $09, $0a, $0b, $0c, $0d, $0e, $0f\r
+    .byte $00, $01, $02, $03, $04, $05, $06, $07, $08, $09, $0a, $0b, $0c, $0d, $0e, $0f\r
+    .byte $00, $01, $02, $03, $04, $05, $06, $07, $08, $09, $0a, $0b, $0c, $0d, $0e, $0f\r
+    .byte $00, $01, $02, $03, $04, $05, $06, $07, $08, $09, $0a, $0b, $0c, $0d, $0e, $0f\r
+    .byte $00, $01, $02, $03, $04, $05, $06, $07, $08, $09, $0a, $0b, $0c, $0d, $0e, $0f\r
+\r
+bl_test4:\r
+    dex\r
+    bpl bl_test3\r
+\r
+;    ;;ora zp, x/abs, x/indir, y\r
+;    lda #$de\r
+;    ldx #$e4\r
+;    sta $a4\r
+;    ;c5|de=df\r
+;    lda #$c5\r
+;    ora $c0, x\r
+;\r
+;    lda #$75\r
+;    stx $0734\r
+;    ;75|e4=f5\r
+;    cmp $0650, x\r
+;\r
+;    ldx #$c9\r
+;    stx $0825\r
+;    lda #$34\r
+;    sta $07\r
+;    lda #$07\r
+;    sta $08\r
+;    ldy #$f1\r
+;    ;page crossing\r
+;    ;07|c9=cf\r
+;    cmp ($07), y\r
+\r
 \r
     ;;done...\r
     ;;infinite loop.\r