// Negative multiplication when NegA xor NegB
bool NegMul = (NegA != NegB);
+ bool HasNeg = NegA || NegB || NegC;
unsigned NewOpcode;
if (!NegMul)
else
NewOpcode = (!NegC) ? X86ISD::FNMADD : X86ISD::FNMSUB;
+ // For FMA and FAMDD, we risk reconstructing the node we started with.
+ // In order to avoid this, we check for negation or opcode change. If
+ // one of the two happened, then it is a new node and we return it.
+ if (N->getOpcode() == X86ISD::FMADD || N->getOpcode() == ISD::FMA) {
+ if (HasNeg || NewOpcode != N->getOpcode())
+ return DAG.getNode(NewOpcode, dl, VT, A, B, C);
+ return SDValue();
+ }
if (N->getOpcode() == X86ISD::FMADD_RND) {
switch (NewOpcode) {
case X86ISD::FNMSUB: NewOpcode = X86ISD::FNMSUBS3_RND; break;
}
} else {
- assert((N->getOpcode() == X86ISD::FMADD || N->getOpcode() == ISD::FMA) &&
- "Unexpected opcode!");
- return DAG.getNode(NewOpcode, dl, VT, A, B, C);
+ llvm_unreachable("Unexpected opcode!");
}
- return DAG.getNode(NewOpcode, dl, VT, A, B, C, N->getOperand(3));
+ // Only return the node is the opcode was changed or one of the
+ // operand was negated. If not, we'll just recreate the same node.
+ if (HasNeg || NewOpcode != N->getOpcode())
+ return DAG.getNode(NewOpcode, dl, VT, A, B, C, N->getOperand(3));
+
+ return SDValue();
}
static SDValue combineZext(SDNode *N, SelectionDAG &DAG,