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drm/amd/display: Update SubVP Visual Confirm
authorDavid Galiffi <David.Galiffi@amd.com>
Sat, 22 Oct 2022 02:22:46 +0000 (22:22 -0400)
committerAlex Deucher <alexander.deucher@amd.com>
Tue, 15 Nov 2022 16:52:55 +0000 (11:52 -0500)
[Why]
The visual confirm bar is displayed on all displays, but is only
updated on a flip. If an update causes SubVP to be disabled on
all displays, but there are no updates on the other displays, it
will lead to stale information displayed on the non-active
displays. An example of this is playing a fullscreen video on a
rotated display.

[How]
Add a procedure to update visual confirm color for all pipes when
committing a plane.

Reviewed-by: Alvin Lee <Alvin.Lee2@amd.com>
Acked-by: Tom Chung <chiahsuan.chung@amd.com>
Signed-off-by: David Galiffi <David.Galiffi@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/display/dc/core/dc.c

index 9f42adc..d90ab18 100644 (file)
@@ -3481,6 +3481,24 @@ static void commit_planes_for_stream(struct dc *dc,
                return;
        }
 
+       if (update_type != UPDATE_TYPE_FAST) {
+               for (j = 0; j < dc->res_pool->pipe_count; j++) {
+                       struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];
+
+                       if (dc->debug.visual_confirm == VISUAL_CONFIRM_SUBVP &&
+                               pipe_ctx->stream && pipe_ctx->plane_state) {
+                               /* Only update visual confirm for SUBVP here.
+                                * The bar appears on all pipes, so we need to update the bar on all displays,
+                                * so the information doesn't get stale.
+                                */
+                               struct mpcc_blnd_cfg blnd_cfg = { 0 };
+
+                               dc->hwss.update_visual_confirm_color(dc, pipe_ctx, &blnd_cfg.black_color,
+                                               pipe_ctx->plane_res.hubp->inst);
+                       }
+               }
+       }
+
        if (!IS_DIAG_DC(dc->ctx->dce_environment)) {
                for (i = 0; i < surface_count; i++) {
                        struct dc_plane_state *plane_state = srf_updates[i].surface;
@@ -3598,7 +3616,6 @@ static void commit_planes_for_stream(struct dc *dc,
                                        dc->hwss.update_plane_addr(dc, pipe_ctx);
                        }
                }
-
        }
 
        if (should_lock_all_pipes && dc->hwss.interdependent_update_lock) {