drm/i915/icl: WaL3BankAddressHashing

Revert to an L3 non-hash model, for performance reasons.

v2:
  - Place the WA name above the actual change
  - Improve the register naming
v3:
  - Rebased
  - Renamed to Wa_1604223664
v4: Rebased on top of the WA refactoring
v5:
  - Added References (Mika)
  - Fixed wrong mask and value (Mika)
  - Do not apply together with another WA for the same
    register (not worth the hassle)
v6:
  - Rebased
  - C, not lisp (Chris)

References: HSDES#1604223664
Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Signed-off-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/1525814984-20039-5-git-send-email-oscar.mateo@intel.com

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index c9c2ad5..81f1a8c 100644 (file)
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -8253,6 +8253,12 @@ enum {
 #define GEN8_GARBCNTL                          _MMIO(0xB004)
 #define   GEN9_GAPS_TSV_CREDIT_DISABLE         (1 << 7)
 #define   GEN11_ARBITRATION_PRIO_ORDER_MASK    (0x3f << 22)
+#define   GEN11_HASH_CTRL_EXCL_MASK            (0x7f << 0)
+#define   GEN11_HASH_CTRL_EXCL_BIT0            (1 << 0)
+
+#define GEN11_GLBLINVL                         _MMIO(0xB404)
+#define   GEN11_BANK_HASH_ADDR_EXCL_MASK       (0x7f << 5)
+#define   GEN11_BANK_HASH_ADDR_EXCL_BIT0       (1 << 5)
 
 #define GEN10_DFR_RATIO_EN_AND_CHICKEN _MMIO(0x9550)
 #define   DFR_DISABLE                  (1 << 9)

diff --git a/drivers/gpu/drm/i915/intel_workarounds.c b/drivers/gpu/drm/i915/intel_workarounds.c
index 44ae0b4..3b03729 100644 (file)
--- a/drivers/gpu/drm/i915/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/intel_workarounds.c
@@ -705,6 +705,16 @@ static void icl_gt_workarounds_apply(struct drm_i915_private *dev_priv)
         */
        I915_WRITE(GEN8_GARBCNTL, I915_READ(GEN8_GARBCNTL) |
                                  GEN11_ARBITRATION_PRIO_ORDER_MASK);
+
+       /* Wa_1604223664:icl
+        * Formerly known as WaL3BankAddressHashing
+        */
+       I915_WRITE(GEN8_GARBCNTL,
+                  (I915_READ(GEN8_GARBCNTL) & ~GEN11_HASH_CTRL_EXCL_MASK) |
+                  GEN11_HASH_CTRL_EXCL_BIT0);
+       I915_WRITE(GEN11_GLBLINVL,
+                  (I915_READ(GEN11_GLBLINVL) & ~GEN11_BANK_HASH_ADDR_EXCL_MASK) |
+                  GEN11_BANK_HASH_ADDR_EXCL_BIT0);
 }
 
 void intel_gt_workarounds_apply(struct drm_i915_private *dev_priv)