Merge branch 'net-dsa-b53-non-legacy'

Russell King says:

====================
net: dsa: b53: convert to phylink_generic_validate() and mark as non-legacy

This series converts b53 to use phylink_generic_validate() and also
marks this driver as non-legacy.

Patch 1 cleans up an if() condition to be more readable before we
proceed with the conversion.

Patch 2 populates the supported_interfaces and mac_capabilities members
of phylink_config.

Patch 3 drops the use of phylink_helper_basex_speed() which is now not
necessary.

Patch 4 switches the driver to use phylink_generic_validate()

Patch 5 marks the driver as non-legacy.
====================

Signed-off-by: David S. Miller <davem@davemloft.net>

diff --git a/drivers/net/dsa/b53/b53_common.c b/drivers/net/dsa/b53/b53_common.c
index a3b9899..83bf303 100644 (file)
--- a/drivers/net/dsa/b53/b53_common.c
+++ b/drivers/net/dsa/b53/b53_common.c
@@ -1309,46 +1309,50 @@ void b53_port_event(struct dsa_switch *ds, int port)
 }
 EXPORT_SYMBOL(b53_port_event);
 
-void b53_phylink_validate(struct dsa_switch *ds, int port,
-                         unsigned long *supported,
-                         struct phylink_link_state *state)
+static void b53_phylink_get_caps(struct dsa_switch *ds, int port,
+                                struct phylink_config *config)
 {
        struct b53_device *dev = ds->priv;
-       __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };
 
-       if (dev->ops->serdes_phylink_validate)
-               dev->ops->serdes_phylink_validate(dev, port, mask, state);
+       /* Internal ports need GMII for PHYLIB */
+       __set_bit(PHY_INTERFACE_MODE_GMII, config->supported_interfaces);
+
+       /* These switches appear to support MII and RevMII too, but beyond
+        * this, the code gives very few clues. FIXME: We probably need more
+        * interface modes here.
+        *
+        * According to b53_srab_mux_init(), ports 3..5 can support:
+        *  SGMII, MII, GMII, RGMII or INTERNAL depending on the MUX setting.
+        * However, the interface mode read from the MUX configuration is
+        * not passed back to DSA, so phylink uses NA.
+        * DT can specify RGMII for ports 0, 1.
+        * For MDIO, port 8 can be RGMII_TXID.
+        */
+       __set_bit(PHY_INTERFACE_MODE_MII, config->supported_interfaces);
+       __set_bit(PHY_INTERFACE_MODE_REVMII, config->supported_interfaces);
 
-       /* Allow all the expected bits */
-       phylink_set(mask, Autoneg);
-       phylink_set_port_modes(mask);
-       phylink_set(mask, Pause);
-       phylink_set(mask, Asym_Pause);
+       config->mac_capabilities = MAC_ASYM_PAUSE | MAC_SYM_PAUSE |
+               MAC_10 | MAC_100;
 
-       /* With the exclusion of 5325/5365, MII, Reverse MII and 802.3z, we
-        * support Gigabit, including Half duplex.
+       /* 5325/5365 are not capable of gigabit speeds, everything else is.
+        * Note: the original code also exclulded Gigagbit for MII, RevMII
+        * and 802.3z modes. MII and RevMII are not able to work above 100M,
+        * so will be excluded by the generic validator implementation.
+        * However, the exclusion of Gigabit for 802.3z just seems wrong.
         */
-       if (state->interface != PHY_INTERFACE_MODE_MII &&
-           state->interface != PHY_INTERFACE_MODE_REVMII &&
-           !phy_interface_mode_is_8023z(state->interface) &&
-           !(is5325(dev) || is5365(dev))) {
-               phylink_set(mask, 1000baseT_Full);
-               phylink_set(mask, 1000baseT_Half);
-       }
+       if (!(is5325(dev) || is5365(dev)))
+               config->mac_capabilities |= MAC_1000;
 
-       if (!phy_interface_mode_is_8023z(state->interface)) {
-               phylink_set(mask, 10baseT_Half);
-               phylink_set(mask, 10baseT_Full);
-               phylink_set(mask, 100baseT_Half);
-               phylink_set(mask, 100baseT_Full);
-       }
+       /* Get the implementation specific capabilities */
+       if (dev->ops->phylink_get_caps)
+               dev->ops->phylink_get_caps(dev, port, config);
 
-       linkmode_and(supported, supported, mask);
-       linkmode_and(state->advertising, state->advertising, mask);
-
-       phylink_helper_basex_speed(state);
+       /* This driver does not make use of the speed, duplex, pause or the
+        * advertisement in its mac_config, so it is safe to mark this driver
+        * as non-legacy.
+        */
+       config->legacy_pre_march2020 = false;
 }
-EXPORT_SYMBOL(b53_phylink_validate);
 
 int b53_phylink_mac_link_state(struct dsa_switch *ds, int port,
                               struct phylink_link_state *state)
@@ -2259,7 +2263,7 @@ static const struct dsa_switch_ops b53_switch_ops = {
        .phy_read               = b53_phy_read16,
        .phy_write              = b53_phy_write16,
        .adjust_link            = b53_adjust_link,
-       .phylink_validate       = b53_phylink_validate,
+       .phylink_get_caps       = b53_phylink_get_caps,
        .phylink_mac_link_state = b53_phylink_mac_link_state,
        .phylink_mac_config     = b53_phylink_mac_config,
        .phylink_mac_an_restart = b53_phylink_mac_an_restart,

diff --git a/drivers/net/dsa/b53/b53_priv.h b/drivers/net/dsa/b53/b53_priv.h
index b41dc8a..a6b339f 100644 (file)
--- a/drivers/net/dsa/b53/b53_priv.h
+++ b/drivers/net/dsa/b53/b53_priv.h
@@ -46,6 +46,8 @@ struct b53_io_ops {
        int (*phy_write16)(struct b53_device *dev, int addr, int reg, u16 value);
        int (*irq_enable)(struct b53_device *dev, int port);
        void (*irq_disable)(struct b53_device *dev, int port);
+       void (*phylink_get_caps)(struct b53_device *dev, int port,
+                                struct phylink_config *config);
        u8 (*serdes_map_lane)(struct b53_device *dev, int port);
        int (*serdes_link_state)(struct b53_device *dev, int port,
                                 struct phylink_link_state *state);
@@ -56,9 +58,6 @@ struct b53_io_ops {
        void (*serdes_link_set)(struct b53_device *dev, int port,
                                unsigned int mode, phy_interface_t interface,
                                bool link_up);
-       void (*serdes_phylink_validate)(struct b53_device *dev, int port,
-                                       unsigned long *supported,
-                                       struct phylink_link_state *state);
 };
 
 #define B53_INVALID_LANE       0xff
@@ -337,9 +336,6 @@ int b53_br_flags(struct dsa_switch *ds, int port,
                 struct netlink_ext_ack *extack);
 int b53_setup_devlink_resources(struct dsa_switch *ds);
 void b53_port_event(struct dsa_switch *ds, int port);
-void b53_phylink_validate(struct dsa_switch *ds, int port,
-                         unsigned long *supported,
-                         struct phylink_link_state *state);
 int b53_phylink_mac_link_state(struct dsa_switch *ds, int port,
                               struct phylink_link_state *state);
 void b53_phylink_mac_config(struct dsa_switch *ds, int port,

diff --git a/drivers/net/dsa/b53/b53_serdes.c b/drivers/net/dsa/b53/b53_serdes.c
index 5ae3d97..555e5b3 100644 (file)
--- a/drivers/net/dsa/b53/b53_serdes.c
+++ b/drivers/net/dsa/b53/b53_serdes.c
@@ -158,9 +158,8 @@ void b53_serdes_link_set(struct b53_device *dev, int port, unsigned int mode,
 }
 EXPORT_SYMBOL(b53_serdes_link_set);
 
-void b53_serdes_phylink_validate(struct b53_device *dev, int port,
-                                unsigned long *supported,
-                                struct phylink_link_state *state)
+void b53_serdes_phylink_get_caps(struct b53_device *dev, int port,
+                                struct phylink_config *config)
 {
        u8 lane = b53_serdes_map_lane(dev, port);
 
@@ -169,16 +168,24 @@ void b53_serdes_phylink_validate(struct b53_device *dev, int port,
 
        switch (lane) {
        case 0:
-               phylink_set(supported, 2500baseX_Full);
+               /* It appears lane 0 supports 2500base-X and 1000base-X */
+               __set_bit(PHY_INTERFACE_MODE_2500BASEX,
+                         config->supported_interfaces);
+               config->mac_capabilities |= MAC_2500FD;
                fallthrough;
        case 1:
-               phylink_set(supported, 1000baseX_Full);
+               /* It appears lane 1 only supports 1000base-X and SGMII */
+               __set_bit(PHY_INTERFACE_MODE_1000BASEX,
+                         config->supported_interfaces);
+               __set_bit(PHY_INTERFACE_MODE_SGMII,
+                         config->supported_interfaces);
+               config->mac_capabilities |= MAC_1000FD;
                break;
        default:
                break;
        }
 }
-EXPORT_SYMBOL(b53_serdes_phylink_validate);
+EXPORT_SYMBOL(b53_serdes_phylink_get_caps);
 
 int b53_serdes_init(struct b53_device *dev, int port)
 {

diff --git a/drivers/net/dsa/b53/b53_serdes.h b/drivers/net/dsa/b53/b53_serdes.h
index 55d280f..f47d5ca 100644 (file)
--- a/drivers/net/dsa/b53/b53_serdes.h
+++ b/drivers/net/dsa/b53/b53_serdes.h
@@ -115,9 +115,8 @@ void b53_serdes_config(struct b53_device *dev, int port, unsigned int mode,
 void b53_serdes_an_restart(struct b53_device *dev, int port);
 void b53_serdes_link_set(struct b53_device *dev, int port, unsigned int mode,
                         phy_interface_t interface, bool link_up);
-void b53_serdes_phylink_validate(struct b53_device *dev, int port,
-                               unsigned long *supported,
-                               struct phylink_link_state *state);
+void b53_serdes_phylink_get_caps(struct b53_device *dev, int port,
+                                struct phylink_config *config);
 #if IS_ENABLED(CONFIG_B53_SERDES)
 int b53_serdes_init(struct b53_device *dev, int port);
 #else

diff --git a/drivers/net/dsa/b53/b53_srab.c b/drivers/net/dsa/b53/b53_srab.c
index 4591bb1..c51b716 100644 (file)
--- a/drivers/net/dsa/b53/b53_srab.c
+++ b/drivers/net/dsa/b53/b53_srab.c
@@ -443,6 +443,39 @@ static void b53_srab_irq_disable(struct b53_device *dev, int port)
        }
 }
 
+static void b53_srab_phylink_get_caps(struct b53_device *dev, int port,
+                                     struct phylink_config *config)
+{
+       struct b53_srab_priv *priv = dev->priv;
+       struct b53_srab_port_priv *p = &priv->port_intrs[port];
+
+       switch (p->mode) {
+       case PHY_INTERFACE_MODE_SGMII:
+#if IS_ENABLED(CONFIG_B53_SERDES)
+               /* If p->mode indicates SGMII mode, that essentially means we
+                * are using a serdes. As the serdes for the capabilities.
+                */
+               b53_serdes_phylink_get_caps(dev, port, config);
+#endif
+               break;
+
+       case PHY_INTERFACE_MODE_NA:
+               break;
+
+       case PHY_INTERFACE_MODE_RGMII:
+               /* If we support RGMII, support all RGMII modes, since
+                * that dictates the PHY delay settings.
+                */
+               phy_interface_set_rgmii(config->supported_interfaces);
+               break;
+
+       default:
+               /* Some other mode (e.g. MII, GMII etc) */
+               __set_bit(p->mode, config->supported_interfaces);
+               break;
+       }
+}
+
 static const struct b53_io_ops b53_srab_ops = {
        .read8 = b53_srab_read8,
        .read16 = b53_srab_read16,
@@ -456,13 +489,13 @@ static const struct b53_io_ops b53_srab_ops = {
        .write64 = b53_srab_write64,
        .irq_enable = b53_srab_irq_enable,
        .irq_disable = b53_srab_irq_disable,
+       .phylink_get_caps = b53_srab_phylink_get_caps,
 #if IS_ENABLED(CONFIG_B53_SERDES)
        .serdes_map_lane = b53_srab_serdes_map_lane,
        .serdes_link_state = b53_serdes_link_state,
        .serdes_config = b53_serdes_config,
        .serdes_an_restart = b53_serdes_an_restart,
        .serdes_link_set = b53_serdes_link_set,
-       .serdes_phylink_validate = b53_serdes_phylink_validate,
 #endif
 };