ARM: take account of possible bundle when erasing an instruction.

Fortunately this appears to be the only ARM-specific pass that runs while
bundles might be in play, so no other cases need modifying.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@273029 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/ARM/Thumb2SizeReduction.cpp b/lib/Target/ARM/Thumb2SizeReduction.cpp
index e1b1266..8df85e9 100644 (file)
--- a/lib/Target/ARM/Thumb2SizeReduction.cpp
+++ b/lib/Target/ARM/Thumb2SizeReduction.cpp
@@ -461,7 +461,7 @@ Thumb2SizeReduce::ReduceLoadStore(MachineBasicBlock &MBB, MachineInstr *MI,
     MIB.setMIFlags(MI->getFlags());
 
     // Kill the old instruction.
-    MI->eraseFromParent();
+    MI->eraseFromBundle();
     ++NumLdSts;
     return true;
   }

diff --git a/test/CodeGen/ARM/thumb2-size-opt.ll b/test/CodeGen/ARM/thumb2-size-opt.ll
index 0084a45..aba0276 100644 (file)
--- a/test/CodeGen/ARM/thumb2-size-opt.ll
+++ b/test/CodeGen/ARM/thumb2-size-opt.ll
@@ -82,3 +82,19 @@ entry:
   %shr = lshr i32 %a, %b
   ret i32 %shr
 }
+
+define i32 @bundled_instruction(i32* %addr, i32** %addr2, i1 %tst) minsize {
+; CHECK-LABEL: bundled_instruction:
+; CHECK: iteee ne
+; CHECK: ldmeq r0!, {{{r[0-9]+}}}
+  br i1 %tst, label %true, label %false
+
+true:
+  ret i32 0
+
+false:
+  %res = load i32, i32* %addr, align 4
+  %next = getelementptr i32, i32* %addr, i32 1
+  store i32* %next, i32** %addr2
+  ret i32 %res
+}