Add support for the MIPS32

diff --git a/bfd/ChangeLog b/bfd/ChangeLog
index 0a987a7..69d43f8 100644 (file)
--- a/bfd/ChangeLog
+++ b/bfd/ChangeLog
@@ -1,3 +1,11 @@
+2000-09-13  Anders Norlander  <anorland@acc.umu.se>
+       
+       * cpu-mips.c (arch_info_struct): Add mips:4K
+       * bfd-in2.h (bfd_mach_mips4K): New define.
+       * archures.c: Add bfd_mach_mips4K to comment.
+       * elf32-mips.c (_bfd_mips_elf_final_write_processing): Return
+       E_MIPS_ARCH_2 for bfd_mach_mips4K.
+
 Wed Sep 13 19:31:39 2000  Marco Franzen <marcof@thyron.com>
 
        * som.c (som_write_symbol_strings): Do not used fixed buffers,

diff --git a/bfd/archures.c b/bfd/archures.c
index 3b68c32..70fa086 100644 (file)
--- a/bfd/archures.c
+++ b/bfd/archures.c
@@ -127,6 +127,7 @@ DESCRIPTION
 .#define bfd_mach_mips6000             6000
 .#define bfd_mach_mips8000             8000
 .#define bfd_mach_mips10000            10000
+.#define bfd_mach_mips4K               32
 .#define bfd_mach_mips16               16
 .  bfd_arch_i386,      {* Intel 386 *}
 .#define bfd_mach_i386_i386 0

diff --git a/bfd/bfd-in2.h b/bfd/bfd-in2.h
index ca6e36b..fe3459f 100644 (file)
--- a/bfd/bfd-in2.h
+++ b/bfd/bfd-in2.h
@@ -1394,6 +1394,7 @@ enum bfd_architecture
 #define bfd_mach_mips8000              8000
 #define bfd_mach_mips10000             10000
 #define bfd_mach_mips16                16
+#define bfd_mach_mips4K                32
   bfd_arch_i386,      /* Intel 386 */
 #define bfd_mach_i386_i386 0
 #define bfd_mach_i386_i8086 1

diff --git a/bfd/cpu-mips.c b/bfd/cpu-mips.c
index c52fbec..8090b7c 100644 (file)
--- a/bfd/cpu-mips.c
+++ b/bfd/cpu-mips.c
@@ -53,6 +53,7 @@ I_mips5000,
 I_mips6000, 
 I_mips8000, 
 I_mips10000,
+I_mips4K,
 I_mips16
 };
 
@@ -75,8 +76,7 @@ static const bfd_arch_info_type arch_info_struct[] =
   N (32, 32, bfd_mach_mips6000, "mips:6000", false, NN(I_mips6000)),
   N (64, 64, bfd_mach_mips8000, "mips:8000", false, NN(I_mips8000)),
   N (64, 64, bfd_mach_mips10000, "mips:10000", false, NN(I_mips10000)),
-
-
+  N (32, 32, bfd_mach_mips4K,   "mips:4K",   false, NN(I_mips4K)),
   N (64, 64, bfd_mach_mips16,   "mips:16",   false, 0),
 };
 

diff --git a/bfd/elf32-mips.c b/bfd/elf32-mips.c
index 5ab839e..fd8847a 100644 (file)
--- a/bfd/elf32-mips.c
+++ b/bfd/elf32-mips.c
@@ -1848,6 +1848,9 @@ elf_mips_mach (flags)
     case E_MIPS_MACH_4650:
       return bfd_mach_mips4650;
 
+    case E_MIPS_MACH_MIPS32:
+      return bfd_mach_mips4K;
+
     default:
       switch (flags & EF_MIPS_ARCH)
        {
@@ -2347,6 +2350,10 @@ _bfd_mips_elf_final_write_processing (abfd, linker)
     case bfd_mach_mips8000:
       val = E_MIPS_ARCH_4;
       break;
+
+    case bfd_mach_mips4K:
+      val = E_MIPS_ARCH_2 | E_MIPS_MACH_MIPS32;
+      break;
     }
 
   elf_elfheader (abfd)->e_flags &= ~ (EF_MIPS_ARCH | EF_MIPS_MACH);

diff --git a/include/elf/ChangeLog b/include/elf/ChangeLog
index 67f3dd4..1256f71 100644 (file)
--- a/include/elf/ChangeLog
+++ b/include/elf/ChangeLog
@@ -1,3 +1,7 @@
+2000-09-13  Anders Norlander  <anorland@acc.umu.se>
+
+       * mips.h (E_MIPS_MACH_4K): New define.
+
 2000-09-05  Alan Modra  <alan@linuxcare.com.au>
 
        * hppa.h: Fix a comment.

diff --git a/include/elf/mips.h b/include/elf/mips.h
index 14ad20f..18185e7 100644 (file)
--- a/include/elf/mips.h
+++ b/include/elf/mips.h
@@ -153,7 +153,9 @@ END_RELOC_NUMBERS (R_MIPS_maxext)
 #define E_MIPS_MACH_4100       0x00830000
 #define E_MIPS_MACH_4650       0x00850000
 #define E_MIPS_MACH_4111       0x00880000
-
+/* -mips32 code.
+   It is easier to treat MIPS32 as a machine rather than an architecture.  */
+#define E_MIPS_MACH_MIPS32     0x00890000
 \f
 /* Processor specific section indices.  These sections do not actually
    exist.  Symbols with a st_shndx field corresponding to one of these

diff --git a/include/opcode/ChangeLog b/include/opcode/ChangeLog
index ac84ae2..73b4dee 100644 (file)
--- a/include/opcode/ChangeLog
+++ b/include/opcode/ChangeLog
@@ -1,3 +1,20 @@
+2000-09-13  Anders Norlander  <anorland@acc.umu.se>
+       
+       * mips.h: Use defines instead of hard-coded processor numbers.
+       (CPU_R2000, CPU_R3000, CPU_R3900, CPU_R4000, CPU_R4010,
+       CPU_VR4100, CPU_R4111, CPU_R4300, CPU_R4400, CPU_R4600, CPU_R4650, 
+       CPU_R5000, CPU_R6000, CPU_R8000, CPU_R10000, CPU_MIPS32, CPU_4K,
+       CPU_4KC, CPU_4KM, CPU_4KP): Define..
+       (OPCODE_IS_MEMBER): Use new defines.
+       (OP_MASK_SEL, OP_SH_SEL): Define.
+       (OP_MASK_CODE20, OP_SH_CODE20): Define.
+       Add 'P' to used characters.
+       Use 'H' for coprocessor select field.
+       Use 'm' for 20 bit breakpoint code.
+       Document new arg characters and add to used characters.
+       (INSN_MIPS32): New define for MIPS32 extensions.
+       (OPCODE_IS_MEMBER): Recognize MIPS32 instructions.
+
 2000-09-05  Alan Modra  <alan@linuxcare.com.au>
 
        * hppa.h: Mention cz completer.

diff --git a/include/opcode/mips.h b/include/opcode/mips.h
index 68fe57a..95415e0 100644 (file)
--- a/include/opcode/mips.h
+++ b/include/opcode/mips.h
@@ -126,6 +126,10 @@ Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  *
 #define OP_MASK_MMISUB          0x1f
 #define OP_MASK_PERFREG                0x1f    /* Performance monitoring */
 #define OP_SH_PERFREG          1
+#define OP_SH_SEL              0       /* Coprocessor select field */
+#define OP_MASK_SEL            0x7     /* The sel field of mfcZ and mtcZ. */
+#define OP_SH_CODE20           6       /* 20 bit breakpoint code */
+#define OP_MASK_CODE20         0xfffff
 
 /* This structure holds information for a particular instruction.  */
 
@@ -172,6 +176,7 @@ struct mips_opcode
    "i" 16 bit unsigned immediate (OP_*_IMMEDIATE)
    "j" 16 bit signed immediate (OP_*_DELTA)
    "k" 5 bit cache opcode in target register position (OP_*_CACHE)
+   "m" 20 bit breakpoint code (OP_*_CODE20)
    "o" 16 bit signed offset (OP_*_DELTA)
    "p" 16 bit PC relative branch target address (OP_*_DELTA)
    "q" 10 bit extra breakpoint code (OP_*_CODE2)
@@ -200,6 +205,7 @@ struct mips_opcode
    "E" 5 bit target register (OP_*_RT)
    "G" 5 bit destination register (OP_*_RD)
    "P" 5 bit performance-monitor register (OP_*_PERFREG)
+   "H" 3 bit sel field (OP_*_SEL)
 
    Macro instructions:
    "A" General 32 bit expression
@@ -215,8 +221,8 @@ struct mips_opcode
 
    Characters used so far, for quick reference when adding more:
    "<>(),"
-   "ABCDEFGILMNSTRVW"
-   "abcdfhijklopqrstuvwxz"
+   "ABCDEFGHILMNPSTRVW"
+   "abcdfhijklmopqrstuvwxz"
 */
 
 /* These are the bits which may be set in the pinfo field of an
@@ -319,10 +325,32 @@ struct mips_opcode
 #define INSN_4100                   0x00000040
 /* Toshiba R3900 instruction.  */
 #define INSN_3900                   0x00000080
-
+/* MIPS32 instruction (4Kc, 4Km, 4Kp).  */
+#define INSN_MIPS32                 0x00000100
 /* 32-bit code running on a ISA3+ CPU. */
 #define INSN_GP32                   0x00001000
 
+/* CPU defines, use instead of hardcoding processor number. Keep this
+   in sync with bfd/archures.c in order for machine selection to work.  */
+#define CPU_R2000      2000
+#define CPU_R3000      3000
+#define CPU_R3900      3900
+#define CPU_R4000      4000
+#define CPU_R4010      4010
+#define CPU_VR4100     4100
+#define CPU_R4111      4111
+#define CPU_R4300      4300
+#define CPU_R4400      4400
+#define CPU_R4600      4600
+#define CPU_R4650      4650
+#define CPU_R5000      5000
+#define CPU_R6000      6000
+#define CPU_R8000      8000
+#define CPU_R10000     10000
+#define CPU_MIPS16     16
+#define CPU_MIPS32     32
+#define CPU_4K         CPU_MIPS32
+
 /* Test for membership in an ISA including chip specific ISAs.
    INSN is pointer to an element of the opcode table; ISA is the
    specified ISA to test against; and CPU is the CPU specific ISA
@@ -331,20 +359,16 @@ struct mips_opcode
    a machine with 64-bit registers; see the documentation under -mgp32
    in the MIPS gas docs. */
 
-#define OPCODE_IS_MEMBER(insn,isa,cpu,gp32)                    \
-    ((((insn)->membership & INSN_ISA) != 0                     \
-      && ((insn)->membership & INSN_ISA) <= isa                        \
-      && ((insn)->membership & INSN_GP32 ? gp32 : 1))          \
-     || (cpu == 4650                                           \
-        && ((insn)->membership & INSN_4650) != 0)              \
-     || (cpu == 4010                                           \
-        && ((insn)->membership & INSN_4010) != 0)              \
-     || ((cpu == 4100                                          \
-         || cpu == 4111                                        \
-         )                                                     \
-        && ((insn)->membership & INSN_4100) != 0)              \
-     || (cpu == 3900                                           \
-        && ((insn)->membership & INSN_3900) != 0))
+#define OPCODE_IS_MEMBER(insn, isa, cpu, gp32)                         \
+    ((((insn)->membership & INSN_ISA) != 0                             \
+      && ((insn)->membership & INSN_ISA) <= (unsigned) isa             \
+      && ((insn)->membership & INSN_GP32 ? gp32 : 1))                  \
+     || (cpu == CPU_R4650 && ((insn)->membership & INSN_4650) != 0)    \
+     || (cpu == CPU_R4010 && ((insn)->membership & INSN_4010) != 0)    \
+     || ((cpu == CPU_VR4100 || cpu == CPU_R4111)                       \
+        && ((insn)->membership & INSN_4100) != 0)                      \
+     || (cpu == CPU_MIPS32 && ((insn)->membership & INSN_MIPS32) != 0) \
+     || (cpu == CPU_R3900  && ((insn)->membership & INSN_3900) != 0))
 
 /* This is a list of macro expanded instructions.
  *

diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 31a0076..69868d0 100644 (file)
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,19 @@
+2000-09-13  Anders Norlander  <anorland@acc.umu.se>
+       
+       * mips-opc.c (mips_builtin_opcodes): Support cache instruction on 4K cores.
+       Add mfc0 and mtc0 with sub-selection values.
+       Add clo and clz opcodes.
+       Add msub and msubu instructions for MIPS32.
+       Add madd/maddu aliases for mad/madu for MIPS32.
+       Support wait, deret, eret, movn, pref for MIPS32.
+       Support tlbp, tlbr, tlbwi, tlbwr.
+       (P4): New define.
+ 
+       * mips-dis.c (print_insn_arg): Print sdbbp 'm' args.
+       (print_insn_arg): Handle 'H' args.
+       (set_mips_isa_type): Recognize 4K.
+       Use CPU_* defines instead of hardcoded numbers.
+
 2000-09-11  Catherine Moore <clm@redhat.com>
 
        * d30v-opc.c (d30v_operand_t): New operand type Rb2.

diff --git a/opcodes/mips-dis.c b/opcodes/mips-dis.c
index fa33821..4c76cde 100644 (file)
--- a/opcodes/mips-dis.c
+++ b/opcodes/mips-dis.c
@@ -177,6 +177,11 @@ print_insn_arg (d, l, pc, info)
                             (l >> OP_SH_CODE2) & OP_MASK_CODE2);
       break;
 
+    case 'm':
+      (*info->fprintf_func) (info->stream, "0x%x",
+                            (l >> OP_SH_CODE20) & OP_MASK_CODE20);
+      break;
+
     case 'C':
       (*info->fprintf_func) (info->stream, "0x%x",
                             (l >> OP_SH_COPZ) & OP_MASK_COPZ);
@@ -235,6 +240,10 @@ print_insn_arg (d, l, pc, info)
                             (l >> OP_SH_PERFREG) & OP_MASK_PERFREG);
       break;
 
+    case 'H':
+      (*info->fprintf_func) (info->stream, "%d", 
+                            (l >> OP_SH_SEL) & OP_MASK_SEL);
+      break;
 
     default:
       /* xgettext:c-format */
@@ -264,71 +273,74 @@ set_mips_isa_type (mach, isa, cputype)
 
   switch (mach)
     {
-      case bfd_mach_mips3000:
-       target_processor = 3000;
-       mips_isa = 1;
-       break;
-      case bfd_mach_mips3900:
-       target_processor = 3900;
-       mips_isa = 1;
-       break;
-      case bfd_mach_mips4000:
-       target_processor = 4000;
-       mips_isa = 3;
-       break;
-      case bfd_mach_mips4010:
-       target_processor = 4010;
-       mips_isa = 2;
-       break;
-      case bfd_mach_mips4100:
-       target_processor = 4100;
-       mips_isa = 3;
-       break;
-      case bfd_mach_mips4111:
-       target_processor = 4100;
-       mips_isa = 3;
-       break;
-      case bfd_mach_mips4300:
-       target_processor = 4300;
-       mips_isa = 3;
-       break;
-      case bfd_mach_mips4400:
-       target_processor = 4400;
-       mips_isa = 3;
-       break;
-      case bfd_mach_mips4600:
-       target_processor = 4600;
-       mips_isa = 3;
-       break;
-      case bfd_mach_mips4650:
-       target_processor = 4650;
-       mips_isa = 3;
-       break;
-      case bfd_mach_mips5000:
-       target_processor = 5000;
-       mips_isa = 4;
-       break;
-      case bfd_mach_mips6000:
-       target_processor = 6000;
-       mips_isa = 2;
-       break;
-      case bfd_mach_mips8000:
-       target_processor = 8000;
-       mips_isa = 4;
-       break;
-      case bfd_mach_mips10000:
-       target_processor = 10000;
-       mips_isa = 4;
-       break;
-      case bfd_mach_mips16:
-       target_processor = 16;
-       mips_isa = 3;
-       break;
-      default:
-       target_processor = 3000;
-       mips_isa = 3;
-       break;
-
+    case bfd_mach_mips3000:
+      target_processor = CPU_R3000;
+      mips_isa = 1;
+      break;
+    case bfd_mach_mips3900:
+      target_processor = CPU_R3900;
+      mips_isa = 1;
+      break;
+    case bfd_mach_mips4000:
+      target_processor = CPU_R4000;
+      mips_isa = 3;
+      break;
+    case bfd_mach_mips4010:
+      target_processor = CPU_R4010;
+      mips_isa = 2;
+      break;
+    case bfd_mach_mips4100:
+      target_processor = CPU_VR4100;
+      mips_isa = 3;
+      break;
+    case bfd_mach_mips4111:
+      target_processor = CPU_VR4100; /* FIXME: Shouldn't this be CPU_R4111 ??? */
+      mips_isa = 3;
+      break;
+    case bfd_mach_mips4300:
+      target_processor = CPU_R4300;
+      mips_isa = 3;
+      break;
+    case bfd_mach_mips4400:
+      target_processor = CPU_R4400;
+      mips_isa = 3;
+      break;
+    case bfd_mach_mips4600:
+      target_processor = CPU_R4600;
+      mips_isa = 3;
+      break;
+    case bfd_mach_mips4650:
+      target_processor = CPU_R4650;
+      mips_isa = 3;
+      break;
+    case bfd_mach_mips4K:
+      target_processor = CPU_4K;
+      mips_isa = 2;
+      break;
+    case bfd_mach_mips5000:
+      target_processor = CPU_R5000;
+      mips_isa = 4;
+      break;
+    case bfd_mach_mips6000:
+      target_processor = CPU_R6000;
+      mips_isa = 2;
+      break;
+    case bfd_mach_mips8000:
+      target_processor = CPU_R8000;
+      mips_isa = 4;
+      break;
+    case bfd_mach_mips10000:
+      target_processor = CPU_R10000;
+      mips_isa = 4;
+      break;
+    case bfd_mach_mips16:
+      target_processor = CPU_MIPS16;
+      mips_isa = 3;
+      break;
+    default:
+      target_processor = CPU_R3000;
+      mips_isa = 3;
+      break;
     }
 
   *isa = mips_isa;

diff --git a/opcodes/mips-opc.c b/opcodes/mips-opc.c
index 40f7ad6..ca42089 100644 (file)
--- a/opcodes/mips-opc.c
+++ b/opcodes/mips-opc.c
@@ -78,6 +78,7 @@ Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  *
 #define I4     INSN_ISA4
 #define I5     INSN_ISA5
 #define P3     INSN_4650
+#define P4     INSN_MIPS32
 #define L1     INSN_4010
 #define V1      INSN_4100
 #define T3      INSN_3900
@@ -317,7 +318,7 @@ const struct mips_opcode mips_builtin_opcodes[] = {
 {"c.ngt.s", "M,S,T",   0x4600003f, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   I4|M1   },
 {"c.ngt.ps","S,T",     0x46c0003f, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   I5      },
 {"c.ngt.ps","M,S,T",   0x46c0003f, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   I5      },
-{"cache",   "k,o(b)",  0xbc000000, 0xfc000000, RD_b,           I3|T3|M1        },
+{"cache",   "k,o(b)",  0xbc000000, 0xfc000000, RD_b,           I3|T3|M1|P4     },
 {"ceil.l.d", "D,S",    0x4620000a, 0xffff003f, WR_D|RD_S|FP_D, I3      },
 {"ceil.l.s", "D,S",    0x4600000a, 0xffff003f, WR_D|RD_S|FP_S, I3      },
 {"ceil.w.d", "D,S",    0x4620000e, 0xffff003f, WR_D|RD_S|FP_D, I2      },
@@ -327,6 +328,8 @@ const struct mips_opcode mips_builtin_opcodes[] = {
 {"cfc1",    "t,S",     0x44400000, 0xffe007ff, LCD|WR_t|RD_C1|FP_S,    I1      },
 {"cfc2",    "t,G",     0x48400000, 0xffe007ff, LCD|WR_t|RD_C2, I1      },
 {"cfc3",    "t,G",     0x4c400000, 0xffe007ff, LCD|WR_t|RD_C3, I1      },
+{"clo",     "d,s",     0x70000021, 0xfc1f07ff, WR_d|RD_s,      P4      },
+{"clz",     "d,s",     0x70000020, 0xfc1f07ff, WR_d|RD_s,      P4      },
 {"ctc0",    "t,G",     0x40c00000, 0xffe007ff, COD|RD_t|WR_CC, I1      },
 {"ctc1",    "t,G",     0x44c00000, 0xffe007ff, COD|RD_t|WR_CC|FP_S,    I1      },
 {"ctc1",    "t,S",     0x44c00000, 0xffe007ff, COD|RD_t|WR_CC|FP_S,    I1      },
@@ -355,7 +358,7 @@ const struct mips_opcode mips_builtin_opcodes[] = {
 /* dctr and dctw are used on the r5000.  */
 {"dctr",    "o(b)",    0xbc050000, 0xfc1f0000, RD_b,   I3      },
 {"dctw",    "o(b)",    0xbc090000, 0xfc1f0000, RD_b,   I3      },
-{"deret",   "",         0x4200001f, 0xffffffff,    0,  G2|M1   },
+{"deret",   "",         0x4200001f, 0xffffffff,    0,  G2|M1|P4        },
 /* For ddiv, see the comments about div.  */
 {"ddiv",    "z,s,t",   0x0000001e, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO,  I3      },
 {"ddiv",    "d,v,t",   0,    (int) M_DDIV_3,   INSN_MACRO,     I3      },
@@ -427,7 +430,7 @@ const struct mips_opcode mips_builtin_opcodes[] = {
 {"dsub",    "d,v,I",   0,    (int) M_DSUB_I,   INSN_MACRO,     I3      },
 {"dsubu",   "d,v,t",   0x0000002f, 0xfc0007ff, WR_d|RD_s|RD_t, I3      },
 {"dsubu",   "d,v,I",   0,    (int) M_DSUBU_I,  INSN_MACRO,     I3      },
-{"eret",    "",                0x42000018, 0xffffffff, 0,      I3|M1   },
+{"eret",    "",                0x42000018, 0xffffffff, 0,      I3|M1|P4        },
 {"floor.l.d", "D,S",   0x4620000b, 0xffff003f, WR_D|RD_S|FP_D, I3      },
 {"floor.l.s", "D,S",   0x4600000b, 0xffff003f, WR_D|RD_S|FP_S, I3      },
 {"floor.w.d", "D,S",   0x4620000f, 0xffff003f, WR_D|RD_S|FP_D, I2      },
@@ -524,19 +527,22 @@ const struct mips_opcode mips_builtin_opcodes[] = {
 {"lwu",     "t,o(b)",  0x9c000000, 0xfc000000, LDD|RD_b|WR_t,  I3      },
 {"lwu",     "t,A(b)",  0,    (int) M_LWU_AB,   INSN_MACRO,     I3      },
 {"lwxc1",   "D,t(b)",  0x4c000000, 0xfc00f83f, LDD|WR_D|RD_t|RD_b,     I4      },
-{"mad",            "s,t",      0x70000000, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO|RD_HI|RD_LO,      P3      },
-{"madu",    "s,t",     0x70000001, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO|RD_HI|RD_LO,      P3      },
+{"mad",            "s,t",      0x70000000, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO|RD_HI|RD_LO,      P3|P4   },
+{"madu",    "s,t",     0x70000001, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO|RD_HI|RD_LO,      P3|P4   },
 {"madd.d",  "D,R,S,T", 0x4c000021, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D,       I4      },
 {"madd.s",  "D,R,S,T", 0x4c000020, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_S,       I4      },
 {"madd.ps", "D,R,S,T", 0x4c000026, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D,       I5      },
 {"madd",    "s,t",     0x0000001c, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO,          L1      },
+{"madd",    "s,t",     0x70000000, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO|RD_HI|RD_LO,      P4      },
 {"madd",    "s,t",     0x70000000, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO|IS_M,             G1|M1   },
 {"madd",    "d,s,t",   0x70000000, 0xfc0007ff, RD_s|RD_t|WR_HI|WR_LO|WR_d|IS_M,        G1      },
 {"maddu",   "s,t",     0x0000001d, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO,          L1      },
+{"maddu",   "s,t",     0x70000001, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO|RD_HI|RD_LO,      P4      },
 {"maddu",   "s,t",     0x70000001, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO|IS_M,     G1|M1},
 {"maddu",   "d,s,t",   0x70000001, 0xfc0007ff, RD_s|RD_t|WR_HI|WR_LO|WR_d|IS_M,        G1},
 {"madd16",  "s,t",      0x00000028, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO|RD_HI|RD_LO,     V1      },
 {"mfc0",    "t,G",     0x40000000, 0xffe007ff, LCD|WR_t|RD_C0, I1      },
+{"mfc0",    "t,G,H",   0x40000000, 0xffe007f8, LCD|WR_t|RD_C0, P4      },
 {"mfc1",    "t,S",     0x44000000, 0xffe007ff, LCD|WR_t|RD_S|FP_S,     I1},
 {"mfc1",    "t,G",     0x44000000, 0xffe007ff, LCD|WR_t|RD_S|FP_S,     I1},
 {"mfc2",    "t,G",     0x48000000, 0xffe007ff, LCD|WR_t|RD_C2, I1      },
@@ -550,7 +556,7 @@ const struct mips_opcode mips_builtin_opcodes[] = {
 {"movf.d",  "D,S,N",   0x46200011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D,   I4|M1   },
 {"movf.s",  "D,S,N",   0x46000011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_S,   I4|M1   },
 {"movf.ps", "D,S,N",   0x46c00011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D,   I5      },
-{"movn",    "d,v,t",   0x0000000b, 0xfc0007ff, WR_d|RD_s|RD_t, I4|M1   },
+{"movn",    "d,v,t",   0x0000000b, 0xfc0007ff, WR_d|RD_s|RD_t, I4|M1|P4        },
 {"ffc",     "d,v",     0x0000000b, 0xfc1f07ff, WR_d|RD_s,L1    },
 {"movn.d",  "D,S,t",   0x46200013, 0xffe0003f, WR_D|RD_S|RD_t|FP_D,    I4|M1   },
 {"movn.s",  "D,S,t",   0x46000013, 0xffe0003f, WR_D|RD_S|RD_t|FP_S,    I4|M1   },
@@ -558,7 +564,7 @@ const struct mips_opcode mips_builtin_opcodes[] = {
 {"movt.d",  "D,S,N",   0x46210011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D,   I4|M1   },
 {"movt.s",  "D,S,N",   0x46010011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_S,   I4|M1   },
 {"movt.ps", "D,S,N",   0x46c10011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D,   I5},
-{"movz",    "d,v,t",   0x0000000a, 0xfc0007ff, WR_d|RD_s|RD_t, I4|M1   },
+{"movz",    "d,v,t",   0x0000000a, 0xfc0007ff, WR_d|RD_s|RD_t, I4|M1|P4        },
 {"ffs",     "d,v",     0x0000000a, 0xfc1f07ff, WR_d|RD_s,L1    },
 {"movz.d",  "D,S,t",   0x46200012, 0xffe0003f, WR_D|RD_S|RD_t|FP_D,    I4|M1   },
 {"movz.s",  "D,S,t",   0x46000012, 0xffe0003f, WR_D|RD_S|RD_t|FP_S,    I4|M1   },
@@ -567,8 +573,11 @@ const struct mips_opcode mips_builtin_opcodes[] = {
 {"msub.s",  "D,R,S,T", 0x4c000028, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_S,       I4      },
 {"msub.ps", "D,R,S,T", 0x4c00002e, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D,       I5      },
 {"msub",    "s,t",     0x0000001e, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO,L1        },
+{"msub",    "s,t",     0x70000004, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO|RD_HI|RD_LO,      P4      },
 {"msubu",   "s,t",     0x0000001f, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO,L1        },
+{"msubu",   "s,t",     0x70000005, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO|RD_HI|RD_LO,      P4      },
 {"mtc0",    "t,G",     0x40800000, 0xffe007ff, COD|RD_t|WR_C0|WR_CC,   I1      },
+{"mtc0",    "t,G,H",   0x40800000, 0xffe007f8, COD|RD_t|WR_C0|WR_CC,   P4      },
 {"mtc1",    "t,S",     0x44800000, 0xffe007ff, COD|RD_t|WR_S|FP_S,     I1      },
 {"mtc1",    "t,G",     0x44800000, 0xffe007ff, COD|RD_t|WR_S|FP_S,     I1      },
 {"mtc2",    "t,G",     0x48800000, 0xffe007ff, COD|RD_t|WR_C2|WR_CC,   I1      },
@@ -578,7 +587,7 @@ const struct mips_opcode mips_builtin_opcodes[] = {
 {"mul.d",   "D,V,T",   0x46200002, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,    I1      },
 {"mul.s",   "D,V,T",   0x46000002, 0xffe0003f, WR_D|RD_S|RD_T|FP_S,    I1      },
 {"mul.ps",  "D,V,T",   0x46c00002, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,    I5      },
-{"mul",     "d,v,t",   0x70000002, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HI|WR_LO,P3},
+{"mul",     "d,v,t",   0x70000002, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HI|WR_LO,     P3|P4   },
 {"mul",     "d,v,t",   0,    (int) M_MUL,      INSN_MACRO,     I1      },
 {"mul",     "d,v,I",   0,    (int) M_MUL_I,    INSN_MACRO,     I1      },
 {"mulo",    "d,v,t",   0,    (int) M_MULO,     INSN_MACRO,     I1      },
@@ -611,7 +620,7 @@ const struct mips_opcode mips_builtin_opcodes[] = {
 {"pll.ps",  "D,V,T",   0x46c0002c, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,    I5},
 {"plu.ps",  "D,V,T",   0x46c0002d, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,    I5},
 
-{"pref",    "k,o(b)",  0xcc000000, 0xfc000000, RD_b,           G3|M1   },
+{"pref",    "k,o(b)",  0xcc000000, 0xfc000000, RD_b,           G3|M1|P4        },
 {"prefx",   "h,t(b)",  0x4c00000f, 0xfc0007ff, RD_b|RD_t,      I4      },
 
 {"pul.ps",  "D,V,T",   0x46c0002e, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,    I5},
@@ -648,6 +657,7 @@ const struct mips_opcode mips_builtin_opcodes[] = {
 {"sdbbp",   "",                0x0000000e, 0xffffffff, TRAP,           G2|M1   },
 {"sdbbp",   "c",       0x0000000e, 0xfc00ffff, TRAP,           G2|M1   },
 {"sdbbp",   "c,q",     0x0000000e, 0xfc00003f, TRAP,           G2|M1   },
+{"sdbbp",   "m",       0x7000003f, 0xfc00003f, TRAP,           P4      },
 {"sdc1",    "T,o(b)",  0xf4000000, 0xfc000000, SM|RD_T|RD_b|FP_D,      I2      },
 {"sdc1",    "E,o(b)",  0xf4000000, 0xfc000000, SM|RD_T|RD_b|FP_D,      I2      },
 {"sdc1",    "T,A(b)",  0,    (int) M_SDC1_AB,  INSN_MACRO,     I2      },
@@ -755,10 +765,10 @@ const struct mips_opcode mips_builtin_opcodes[] = {
 {"tgeu",    "s,t,q",   0x00000031, 0xfc00003f, RD_s|RD_t|TRAP, I2       },
 {"tgeu",    "s,j",     0x04090000, 0xfc1f0000, RD_s|TRAP,      I2              }, /* tgeiu */
 {"tgeu",    "s,I",     0,    (int) M_TGEU_I,   INSN_MACRO,     I2      },
-{"tlbp",    "",                0x42000008, 0xffffffff, INSN_TLB,       I1|M1   },
-{"tlbr",    "",                0x42000001, 0xffffffff, INSN_TLB,       I1|M1   },
-{"tlbwi",   "",                0x42000002, 0xffffffff, INSN_TLB,       I1|M1   },
-{"tlbwr",   "",                0x42000006, 0xffffffff, INSN_TLB,       I1|M1   },
+{"tlbp",    "",                0x42000008, 0xffffffff, INSN_TLB,       I1|M1|P4        },
+{"tlbr",    "",                0x42000001, 0xffffffff, INSN_TLB,       I1|M1|P4        },
+{"tlbwi",   "",                0x42000002, 0xffffffff, INSN_TLB,       I1|M1|P4        },
+{"tlbwr",   "",                0x42000006, 0xffffffff, INSN_TLB,       I1|M1|P4        },
 {"tlti",    "s,j",     0x040a0000, 0xfc1f0000, RD_s|TRAP,      I2              },
 {"tlt",     "s,t",     0x00000032, 0xfc00ffff, RD_s|RD_t|TRAP, I2       },
 {"tlt",     "s,t,q",   0x00000032, 0xfc00003f, RD_s|RD_t|TRAP, I2       },
@@ -799,7 +809,7 @@ const struct mips_opcode mips_builtin_opcodes[] = {
 {"xor",     "d,v,t",   0x00000026, 0xfc0007ff, WR_d|RD_s|RD_t, I1      },
 {"xor",     "t,r,I",   0,    (int) M_XOR_I,    INSN_MACRO,     I1      },
 {"xori",    "t,r,i",   0x38000000, 0xfc000000, WR_t|RD_s,      I1      },
-{"wait",    "",                0x42000020, 0xffffffff, TRAP,   I3|M1   },
+{"wait",    "",                0x42000020, 0xffffffff, TRAP,   I3|M1|P4        },
 {"waiti",   "",                0x42000020, 0xffffffff, TRAP,   L1      },
 {"wb",             "o(b)",     0xbc040000, 0xfc1f0000, SM|RD_b,        L1      },
 /* No hazard protection on coprocessor instructions--they shouldn't