- sty abs supported

- rti supported.
- test case updated.

diff --git a/simulation/cpu/decoder.vhd b/simulation/cpu/decoder.vhd
index 3ed5704..3d81106 100644 (file)
--- a/simulation/cpu/decoder.vhd
+++ b/simulation/cpu/decoder.vhd
@@ -1703,6 +1703,10 @@ end  procedure;
                 elsif instruction  = conv_std_logic_vector(16#8c#, dsize) then
                     --abs
                     d_print("sty");
+                    a3_abs;
+                    if exec_cycle = T3 then
+                        front_oe(y_cmd, '0');
+                    end if;
 
 
                 ----------------------------------------
@@ -1937,6 +1941,73 @@ end  procedure;
                 -- A.5.5 return from interrupt
                 ----------------------------------------
                 elsif instruction = conv_std_logic_vector(16#40#, dsize) then
+                    if exec_cycle = T1 then
+                        d_print("rti 2");
+                        fetch_stop;
+
+                        --pop stack (decrement only)
+                        back_oe(sp_cmd, '0');
+                        back_we(sp_cmd, '0');
+                        sp_pop_n <= '0';
+                        sp_oe_n <= '0';
+
+                        next_cycle <= T2;
+                    elsif exec_cycle = T2 then
+                        d_print("rti 3");
+
+                        --pop p (status)
+                        back_oe(sp_cmd, '0');
+                        back_we(sp_cmd, '0');
+                        sp_pop_n <= '0';
+                        sp_oe_n <= '0';
+
+                        --load status reg
+                        stat_dec_oe_n <= '1';
+                        dbuf_int_oe_n <= '0';
+                        stat_bus_all_n <= '0';
+
+                        next_cycle <= T3;
+                    elsif exec_cycle = T3 then
+                        d_print("rti 4");
+                        stat_bus_all_n <= '1';
+
+                        --pop pcl
+                        back_oe(sp_cmd, '0');
+                        back_we(sp_cmd, '0');
+                        sp_pop_n <= '0';
+                        sp_oe_n <= '0';
+
+                        --load lo addr.
+                        dbuf_int_oe_n <= '0';
+                        front_we(pcl_cmd, '0');
+
+                        next_cycle <= T4;
+                    elsif exec_cycle = T4 then
+                        d_print("rti 5");
+                        --stack decrement stop.
+                        back_we(sp_cmd, '1');
+                        sp_pop_n <= '1';
+                        front_we(pcl_cmd, '1');
+
+                        --pop pch
+                        back_oe(sp_cmd, '0');
+                        sp_oe_n <= '0';
+                        --load hi addr.
+                        dbuf_int_oe_n <= '0';
+                        front_we(pch_cmd, '0');
+
+                        next_cycle <= T5;
+                    elsif exec_cycle = T5 then
+                        d_print("rti 5");
+                        back_oe(sp_cmd, '1');
+                        sp_oe_n <= '1';
+                        --load hi addr.
+                        dbuf_int_oe_n <= '1';
+                        front_we(pch_cmd, '1');
+
+                        --increment pc.
+                        next_cycle <= T0;
+                    end if; --if exec_cycle = T1 then
 
                 ----------------------------------------
                 -- A.5.6 jmp

diff --git a/tools/test-image/sample1.asm b/tools/test-image/sample1.asm
index 213485b..5c17b22 100644 (file)
--- a/tools/test-image/sample1.asm
+++ b/tools/test-image/sample1.asm
@@ -348,6 +348,122 @@ boundary_3_4:
     ;;;@88fd\r
        sta     $06fc, x\r
 \r
+\r
+    ;;;;test...\r
+    STY   $0720\r
+    LDY   #$80\r
+    STY   $0721\r
+    ASL   \r
+    ASL   \r
+    ASL   \r
+    ASL   \r
+    STA   $06a0\r
+    DEC   $0730\r
+    DEC   $0731\r
+    DEC   $0732\r
+    LDA   #$0b\r
+    STA   $071e\r
+    ;;JSR   $9c22\r
+    LDA   $0750\r
+    ;;JSR   $9c09\r
+    AND   #$60\r
+    ASL   \r
+    ROL   \r
+    ROL   \r
+    ROL   \r
+    STA   $074e\r
+    ;;RTS   \r
+    TAY   \r
+    LDA   $0750\r
+    AND   #$1f\r
+    STA   $074f\r
+    LDA   $9ce0, y\r
+    CLC   \r
+    ADC   $074f\r
+    TAY   \r
+    LDA   $9ce4, y\r
+    STA   $e9\r
+    LDA   $9d06, y\r
+    STA   $ea\r
+    LDY   $074e\r
+    LDA   $9d28, y\r
+    CLC   \r
+    ADC   $074f\r
+    TAY   \r
+    LDA   $9d2c, y\r
+    STA   $e7\r
+    LDA   $9d4e, y\r
+    STA   $e8\r
+    LDY   #$00\r
+    LDA   ($e7), y\r
+    PHA   \r
+    AND   #$07\r
+    CMP   #$04\r
+    ;;BCC   +5\r
+    STA   $0741\r
+    PLA   \r
+    PHA   \r
+    AND   #$38\r
+    LSR   \r
+    LSR   \r
+    LSR   \r
+    STA   $0710\r
+    PLA   \r
+    AND   #$c0\r
+    CLC   \r
+    ROL   \r
+    ROL   \r
+    ROL   \r
+    STA   $0715\r
+    INY   \r
+    LDA   ($e7), y\r
+    PHA   \r
+    AND   #$0f\r
+    STA   $0727\r
+    PLA   \r
+    PHA   \r
+    AND   #$30\r
+    LSR   \r
+    LSR   \r
+    LSR   \r
+    LSR   \r
+    STA   $0742\r
+    PLA   \r
+    AND   #$c0\r
+    CLC   \r
+    ROL   \r
+    ROL   \r
+    ROL   \r
+    CMP   #$03\r
+    ;;BNE   5\r
+    STA   $0733\r
+    LDA   $e7\r
+    CLC   \r
+    ADC   #$02\r
+    STA   $e7\r
+    LDA   $e8\r
+    ADC   #$00\r
+    STA   $e8\r
+    ;;RTS   \r
+    LDA   $076a\r
+    ;;BNE   16\r
+    LDA   $075f\r
+    CMP   #$04\r
+    ;BCC   12\r
+    LDA   $075b\r
+    ;;BEQ   5\r
+    LDA   #$80\r
+    STA   $fb\r
+    LDA   #$01\r
+    STA   $0774\r
+    INC   $0772\r
+    ;;RTS   \r
+    LDA   $2002\r
+    PLA   \r
+    ORA   #$80\r
+    STA   $2000\r
+    rti\r
+\r
     nop\r
     nop\r
     nop\r