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drm/amdgpu: added support 2nd UVD instance
authorEvan Quan <evan.quan@amd.com>
Tue, 14 Aug 2018 18:53:52 +0000 (14:53 -0400)
committerAlex Deucher <alexander.deucher@amd.com>
Mon, 27 Aug 2018 16:10:49 +0000 (11:10 -0500)
Added psp fw loading support for vega20 2nd UVD instance.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Acked-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Feifei Xu <Feifei.Xu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h
drivers/gpu/drm/amd/amdgpu/psp_gfx_if.h
drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c

index a1edc70..b358e75 100644 (file)
@@ -193,6 +193,7 @@ enum AMDGPU_UCODE_ID {
        AMDGPU_UCODE_ID_STORAGE,
        AMDGPU_UCODE_ID_SMC,
        AMDGPU_UCODE_ID_UVD,
+       AMDGPU_UCODE_ID_UVD1,
        AMDGPU_UCODE_ID_VCE,
        AMDGPU_UCODE_ID_VCN,
        AMDGPU_UCODE_ID_MAXIMUM,
index 0cf48d2..882bd83 100644 (file)
@@ -189,7 +189,8 @@ enum psp_gfx_fw_type
     GFX_FW_TYPE_RLC_RESTORE_LIST_GPM_MEM        = 20,
     GFX_FW_TYPE_RLC_RESTORE_LIST_SRM_MEM        = 21,
     GFX_FW_TYPE_RLC_RESTORE_LIST_CNTL           = 22,
-    GFX_FW_TYPE_MAX         = 23
+    GFX_FW_TYPE_UVD1        = 23,
+    GFX_FW_TYPE_MAX         = 24
 };
 
 /* Command to load HW IP FW. */
index 9c58a23..b70cfa3 100644 (file)
@@ -81,6 +81,9 @@ psp_v11_0_get_fw_type(struct amdgpu_firmware_info *ucode, enum psp_gfx_fw_type *
        case AMDGPU_UCODE_ID_VCE:
                *type = GFX_FW_TYPE_VCE;
                break;
+       case AMDGPU_UCODE_ID_UVD1:
+               *type = GFX_FW_TYPE_UVD1;
+               break;
        case AMDGPU_UCODE_ID_MAXIMUM:
        default:
                return -EINVAL;
index e334255..79cb378 100644 (file)
@@ -441,6 +441,13 @@ static int uvd_v7_0_sw_init(void *handle)
                adev->firmware.ucode[AMDGPU_UCODE_ID_UVD].fw = adev->uvd.fw;
                adev->firmware.fw_size +=
                        ALIGN(le32_to_cpu(hdr->ucode_size_bytes), PAGE_SIZE);
+
+               if (adev->uvd.num_uvd_inst == UVD7_MAX_HW_INSTANCES_VEGA20) {
+                       adev->firmware.ucode[AMDGPU_UCODE_ID_UVD1].ucode_id = AMDGPU_UCODE_ID_UVD1;
+                       adev->firmware.ucode[AMDGPU_UCODE_ID_UVD1].fw = adev->uvd.fw;
+                       adev->firmware.fw_size +=
+                               ALIGN(le32_to_cpu(hdr->ucode_size_bytes), PAGE_SIZE);
+               }
                DRM_INFO("PSP loading UVD firmware\n");
        }