powerpc/mm: Switch obsolete dssall to .long

The dssall ("Data Stream Stop All") instruction is obsolete altogether
with other Data Cache Instructions since ISA 2.03 (year 2006).

LLVM IAS does not support it but PPC970 seems to be using it.
This switches dssall to .long as there is no much point in fixing LLVM.

Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/20211221055904.555763-6-aik@ozlabs.ru

diff --git a/arch/powerpc/include/asm/ppc-opcode.h b/arch/powerpc/include/asm/ppc-opcode.h
index f50213e..9fe3223 100644 (file)
--- a/arch/powerpc/include/asm/ppc-opcode.h
+++ b/arch/powerpc/include/asm/ppc-opcode.h
@@ -249,6 +249,7 @@
 #define PPC_INST_COPY                  0x7c20060c
 #define PPC_INST_DCBA                  0x7c0005ec
 #define PPC_INST_DCBA_MASK             0xfc0007fe
+#define PPC_INST_DSSALL                        0x7e00066c
 #define PPC_INST_ISEL                  0x7c00001e
 #define PPC_INST_ISEL_MASK             0xfc00003e
 #define PPC_INST_LSWI                  0x7c0004aa
@@ -577,6 +578,7 @@
 #define        PPC_DCBZL(a, b)         stringify_in_c(.long PPC_RAW_DCBZL(a, b))
 #define        PPC_DIVDE(t, a, b)      stringify_in_c(.long PPC_RAW_DIVDE(t, a, b))
 #define        PPC_DIVDEU(t, a, b)     stringify_in_c(.long PPC_RAW_DIVDEU(t, a, b))
+#define PPC_DSSALL             stringify_in_c(.long PPC_INST_DSSALL)
 #define PPC_LQARX(t, a, b, eh) stringify_in_c(.long PPC_RAW_LQARX(t, a, b, eh))
 #define PPC_STQCX(t, a, b)     stringify_in_c(.long PPC_RAW_STQCX(t, a, b))
 #define PPC_MADDHD(t, a, b, c) stringify_in_c(.long PPC_RAW_MADDHD(t, a, b, c))

diff --git a/arch/powerpc/kernel/idle.c b/arch/powerpc/kernel/idle.c
index 1f83553..4ad79eb 100644 (file)
--- a/arch/powerpc/kernel/idle.c
+++ b/arch/powerpc/kernel/idle.c
@@ -82,7 +82,7 @@ void power4_idle(void)
                return;
 
        if (cpu_has_feature(CPU_FTR_ALTIVEC))
-               asm volatile("DSSALL ; sync" ::: "memory");
+               asm volatile(PPC_DSSALL " ; sync" ::: "memory");
 
        power4_idle_nap();
 

diff --git a/arch/powerpc/kernel/idle_6xx.S b/arch/powerpc/kernel/idle_6xx.S
index 13cad92..3c09735 100644 (file)
--- a/arch/powerpc/kernel/idle_6xx.S
+++ b/arch/powerpc/kernel/idle_6xx.S
@@ -129,7 +129,7 @@ BEGIN_FTR_SECTION
 END_FTR_SECTION_IFCLR(CPU_FTR_NO_DPM)
        mtspr   SPRN_HID0,r4
 BEGIN_FTR_SECTION
-       DSSALL
+       PPC_DSSALL
        sync
 END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
        lwz     r8,TI_LOCAL_FLAGS(r2)   /* set napping bit */

diff --git a/arch/powerpc/kernel/l2cr_6xx.S b/arch/powerpc/kernel/l2cr_6xx.S
index 225511d..f2e03ed 100644 (file)
--- a/arch/powerpc/kernel/l2cr_6xx.S
+++ b/arch/powerpc/kernel/l2cr_6xx.S
@@ -96,7 +96,7 @@ END_FTR_SECTION_IFCLR(CPU_FTR_L2CR)
 
        /* Stop DST streams */
 BEGIN_FTR_SECTION
-       DSSALL
+       PPC_DSSALL
        sync
 END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
 
@@ -292,7 +292,7 @@ END_FTR_SECTION_IFCLR(CPU_FTR_L3CR)
        isync
 
        /* Stop DST streams */
-       DSSALL
+       PPC_DSSALL
        sync
 
        /* Get the current enable bit of the L3CR into r4 */
@@ -401,7 +401,7 @@ END_FTR_SECTION_IFSET(CPU_FTR_L3CR)
 _GLOBAL(__flush_disable_L1)
        /* Stop pending alitvec streams and memory accesses */
 BEGIN_FTR_SECTION
-       DSSALL
+       PPC_DSSALL
 END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
        sync
 

diff --git a/arch/powerpc/kernel/swsusp_32.S b/arch/powerpc/kernel/swsusp_32.S
index f73f4d7..e0cbd63 100644 (file)
--- a/arch/powerpc/kernel/swsusp_32.S
+++ b/arch/powerpc/kernel/swsusp_32.S
@@ -181,7 +181,7 @@ _GLOBAL(swsusp_arch_resume)
 #ifdef CONFIG_ALTIVEC
        /* Stop pending alitvec streams and memory accesses */
 BEGIN_FTR_SECTION
-       DSSALL
+       PPC_DSSALL
 END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
 #endif
        sync

diff --git a/arch/powerpc/kernel/swsusp_asm64.S b/arch/powerpc/kernel/swsusp_asm64.S
index 96bb207..9f1903c 100644 (file)
--- a/arch/powerpc/kernel/swsusp_asm64.S
+++ b/arch/powerpc/kernel/swsusp_asm64.S
@@ -141,7 +141,7 @@ END_FW_FTR_SECTION_IFCLR(FW_FEATURE_LPAR)
 _GLOBAL(swsusp_arch_resume)
        /* Stop pending alitvec streams and memory accesses */
 BEGIN_FTR_SECTION
-       DSSALL
+       PPC_DSSALL
 END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
        sync
 

diff --git a/arch/powerpc/mm/mmu_context.c b/arch/powerpc/mm/mmu_context.c
index 735c36f..1fb9c99 100644 (file)
--- a/arch/powerpc/mm/mmu_context.c
+++ b/arch/powerpc/mm/mmu_context.c
@@ -90,7 +90,7 @@ void switch_mm_irqs_off(struct mm_struct *prev, struct mm_struct *next,
         * context
         */
        if (cpu_has_feature(CPU_FTR_ALTIVEC))
-               asm volatile ("dssall");
+               asm volatile (PPC_DSSALL);
 
        if (!new_on_cpu)
                membarrier_arch_switch_mm(prev, next, tsk);

diff --git a/arch/powerpc/platforms/powermac/cache.S b/arch/powerpc/platforms/powermac/cache.S
index ced2254..b8ae56e 100644 (file)
--- a/arch/powerpc/platforms/powermac/cache.S
+++ b/arch/powerpc/platforms/powermac/cache.S
@@ -48,7 +48,7 @@ flush_disable_75x:
 
        /* Stop DST streams */
 BEGIN_FTR_SECTION
-       DSSALL
+       PPC_DSSALL
        sync
 END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
 
@@ -197,7 +197,7 @@ flush_disable_745x:
        isync
 
        /* Stop prefetch streams */
-       DSSALL
+       PPC_DSSALL
        sync
 
        /* Disable L2 prefetching */