drm/amd/powerplay: implement uvd & vce dpm enable functions

add dpm enable functions for vce,uvd.

Signed-off-by: Kevin Wang <kevin1.wang@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
index 101f04d..955b350 100644 (file)
--- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
@@ -514,6 +514,8 @@ struct smu_funcs
        int (*update_od8_settings)(struct smu_context *smu,
                                   uint32_t index,
                                   uint32_t value);
+       int (*dpm_set_uvd_enable)(struct smu_context *smu, bool enable);
+       int (*dpm_set_vce_enable)(struct smu_context *smu, bool enable);
 };
 
 #define smu_init_microcode(smu) \
@@ -659,6 +661,10 @@ struct smu_funcs
        ((smu)->funcs->notify_smu_enable_pwe ? (smu)->funcs->notify_smu_enable_pwe((smu)) : 0)
 #define smu_set_watermarks_for_clock_ranges(smu, clock_ranges) \
        ((smu)->funcs->set_watermarks_for_clock_ranges ? (smu)->funcs->set_watermarks_for_clock_ranges((smu), (clock_ranges)) : 0)
+#define smu_dpm_set_uvd_enable(smu, enable) \
+       ((smu)->funcs->dpm_set_uvd_enable ? (smu)->funcs->dpm_set_uvd_enable((smu), (enable)) : 0)
+#define smu_dpm_set_vce_enable(smu, enable) \
+       ((smu)->funcs->dpm_set_vce_enable ? (smu)->funcs->dpm_set_vce_enable((smu), (enable)) : 0)
 
 
 extern int smu_get_atom_data_table(struct smu_context *smu, uint32_t table,

diff --git a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
index 400d981..cdaf23f 100644 (file)
--- a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
+++ b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
@@ -1590,6 +1590,28 @@ static int smu_v11_0_update_od8_settings(struct smu_context *smu,
        return 0;
 }
 
+static int smu_v11_0_dpm_set_uvd_enable(struct smu_context *smu, bool enable)
+{
+       if (!smu_feature_is_supported(smu, FEATURE_DPM_VCE_BIT))
+               return 0;
+
+       if (enable == smu_feature_is_enabled(smu, FEATURE_DPM_VCE_BIT))
+               return 0;
+
+       return smu_feature_set_enabled(smu, FEATURE_DPM_VCE_BIT, enable);
+}
+
+static int smu_v11_0_dpm_set_vce_enable(struct smu_context *smu, bool enable)
+{
+       if (!smu_feature_is_supported(smu, FEATURE_DPM_UVD_BIT))
+               return 0;
+
+       if (enable == smu_feature_is_enabled(smu, FEATURE_DPM_UVD_BIT))
+               return 0;
+
+       return smu_feature_set_enabled(smu, FEATURE_DPM_UVD_BIT, enable);
+}
+
 static const struct smu_funcs smu_v11_0_funcs = {
        .init_microcode = smu_v11_0_init_microcode,
        .load_microcode = smu_v11_0_load_microcode,
@@ -1635,6 +1657,9 @@ static const struct smu_funcs smu_v11_0_funcs = {
        .get_power_profile_mode = smu_v11_0_get_power_profile_mode,
        .set_power_profile_mode = smu_v11_0_set_power_profile_mode,
        .update_od8_settings = smu_v11_0_update_od8_settings,
+       .dpm_set_uvd_enable = smu_v11_0_dpm_set_uvd_enable,
+       .dpm_set_vce_enable = smu_v11_0_dpm_set_vce_enable,
+
 };
 
 void smu_v11_0_set_smu_funcs(struct smu_context *smu)