startpfn = atop(CKSEG0_TO_PHYS((vaddr_t)&end) + PAGE_SIZE);
endpfn = atop(96 << 20);
- mem_layout->mem_first_page = startpfn;
- mem_layout->mem_last_page = endpfn;
- mem_layout->mem_freelist = VM_FREELIST_DEFAULT;
+ mem_layout[0].mem_first_page = startpfn;
+ mem_layout[0].mem_last_page = endpfn;
+ mem_layout[0].mem_freelist = VM_FREELIST_DEFAULT;
physmem = endpfn - startpfn;
uint32_t realmem_bytes;
phys_avail[1] = realmem_bytes;
realmem_bytes -= OCTEON_DRAM_FIRST_256_END;
realmem_bytes &= ~(PAGE_SIZE - 1);
+ mem_layout[0].mem_last_page = atop(phys_avail[1]);
} else {
/* Simulator gets 96Meg period. */
phys_avail[1] = (96 << 20);
*
*/
physmem = btoc(phys_avail[1] - phys_avail[0]);
+
if ((octeon_board_real()) &&
(realmem_bytes > OCTEON_DRAM_FIRST_256_END)) {
/* take out the upper non-cached 1/2 */
phys_avail[2] = 0x20000000;
phys_avail[3] = ((uint32_t) 0x20000000 + realmem_bytes);
physmem += btoc(phys_avail[3] - phys_avail[2]);
+ mem_layout[1].mem_first_page = atop(phys_avail[2]);
+ mem_layout[1].mem_last_page = atop(phys_avail[3]-1);
+ mem_layout[1].mem_freelist = VM_FREELIST_DEFAULT;
}
realmem = physmem;
-
printf("Total DRAM Size %#X\n", (uint32_t) octeon_dram);
- printf("Bank 0 = %#08lX -> %#08lX\n", (long)phys_avail[0], (long)phys_avail[1]);
- printf("Bank 1 = %#08lX -> %#08lX\n", (long)phys_avail[2], (long)phys_avail[3]);
+ printf("Bank 0 = %08lX -> %08lX\n", (long)phys_avail[0], (long)phys_avail[1]);
+ printf("Bank 1 = %08lX -> %08lX\n", (long)phys_avail[2], (long)phys_avail[3]);
+
}
/*