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drm/i915/bdw: Add missing delay during L3 SQC credit programming
author
Imre Deak
<imre.deak@intel.com>
Tue, 3 May 2016 12:54:19 +0000
(15:54 +0300)
committer
Jani Nikula
<jani.nikula@intel.com>
Wed, 4 May 2016 06:48:15 +0000
(09:48 +0300)
BSpec requires us to wait ~100 clocks before re-enabling clock gating,
so make sure we do this.
CC: stable@vger.kernel.org
CC: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link:
http://patchwork.freedesktop.org/patch/msgid/1462280061-1457-2-git-send-email-imre.deak@intel.com
(cherry picked from commit
48e5d68d28f00c0cadac5a830980ff3222781abb
)
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
drivers/gpu/drm/i915/intel_pm.c
patch
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diff --git
a/drivers/gpu/drm/i915/intel_pm.c
b/drivers/gpu/drm/i915/intel_pm.c
index
8ed3cf3
..
3425d8e
100644
(file)
--- a/
drivers/gpu/drm/i915/intel_pm.c
+++ b/
drivers/gpu/drm/i915/intel_pm.c
@@
-6646,6
+6646,12
@@
static void broadwell_init_clock_gating(struct drm_device *dev)
misccpctl = I915_READ(GEN7_MISCCPCTL);
I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
I915_WRITE(GEN8_L3SQCREG1, BDW_WA_L3SQCREG1_DEFAULT);
+ /*
+ * Wait at least 100 clocks before re-enabling clock gating. See
+ * the definition of L3SQCREG1 in BSpec.
+ */
+ POSTING_READ(GEN8_L3SQCREG1);
+ udelay(1);
I915_WRITE(GEN7_MISCCPCTL, misccpctl);
/*