[v1.0][Schematic] Add PIC18F46K20 (DIP).

diff --git a/gSCH/libs/PIC18F46K20_DIP40.sym b/gSCH/libs/PIC18F46K20_DIP40.sym
new file mode 100644 (file)
index 0000000..19e1b78
--- /dev/null
+++ b/gSCH/libs/PIC18F46K20_DIP40.sym
@@ -0,0 +1,462 @@
+v 20131024 2
+P 0 6000 300 6000 1 0 0
+{
+T 200 6050 5 8 1 1 0 6 1
+pinnumber=1
+T 200 5950 5 8 0 1 0 8 1
+pinseq=1
+T 350 6000 9 8 1 1 0 0 1
+pinlabel=_MCLR_/VPP/RE3
+T 350 6000 5 8 0 1 0 2 1
+pintype=io
+}
+P 0 5700 300 5700 1 0 0
+{
+T 200 5750 5 8 1 1 0 6 1
+pinnumber=2
+T 200 5650 5 8 0 1 0 8 1
+pinseq=2
+T 350 5700 9 8 1 1 0 0 1
+pinlabel=RA0/AN0/C12IN0-
+T 350 5700 5 8 0 1 0 2 1
+pintype=io
+}
+P 0 5400 300 5400 1 0 0
+{
+T 200 5450 5 8 1 1 0 6 1
+pinnumber=3
+T 200 5350 5 8 0 1 0 8 1
+pinseq=3
+T 350 5400 9 8 1 1 0 0 1
+pinlabel=RA1/AN1/C12IN1-
+T 350 5400 5 8 0 1 0 2 1
+pintype=io
+}
+P 0 5100 300 5100 1 0 0
+{
+T 200 5150 5 8 1 1 0 6 1
+pinnumber=4
+T 200 5050 5 8 0 1 0 8 1
+pinseq=4
+T 350 5100 9 8 1 1 0 0 1
+pinlabel=RA2/AN2/VREF-/CVREF/C2IN+
+T 350 5100 5 8 0 1 0 2 1
+pintype=io
+}
+P 0 4800 300 4800 1 0 0
+{
+T 200 4850 5 8 1 1 0 6 1
+pinnumber=5
+T 200 4750 5 8 0 1 0 8 1
+pinseq=5
+T 350 4800 9 8 1 1 0 0 1
+pinlabel=RA3/AN3/VREF+/C1IN+
+T 350 4800 5 8 0 1 0 2 1
+pintype=io
+}
+P 0 4500 300 4500 1 0 0
+{
+T 200 4550 5 8 1 1 0 6 1
+pinnumber=6
+T 200 4450 5 8 0 1 0 8 1
+pinseq=6
+T 350 4500 9 8 1 1 0 0 1
+pinlabel=RA4/T0CKI/C1OUT
+T 350 4500 5 8 0 1 0 2 1
+pintype=io
+}
+P 0 4200 300 4200 1 0 0
+{
+T 200 4250 5 8 1 1 0 6 1
+pinnumber=7
+T 200 4150 5 8 0 1 0 8 1
+pinseq=7
+T 350 4200 9 8 1 1 0 0 1
+pinlabel=RA5/AN4/_SS_/HLVDIN/C2OUT
+T 350 4200 5 8 0 1 0 2 1
+pintype=io
+}
+P 0 3900 300 3900 1 0 0
+{
+T 200 3950 5 8 1 1 0 6 1
+pinnumber=8
+T 200 3850 5 8 0 1 0 8 1
+pinseq=8
+T 350 3900 9 8 1 1 0 0 1
+pinlabel=RE0/_RD_/AN5
+T 350 3900 5 8 0 1 0 2 1
+pintype=io
+}
+P 0 3600 300 3600 1 0 0
+{
+T 200 3650 5 8 1 1 0 6 1
+pinnumber=9
+T 200 3550 5 8 0 1 0 8 1
+pinseq=9
+T 350 3600 9 8 1 1 0 0 1
+pinlabel=RE1/_WR_/AN6
+T 350 3600 5 8 0 1 0 2 1
+pintype=io
+}
+P 0 3300 300 3300 1 0 0
+{
+T 200 3350 5 8 1 1 0 6 1
+pinnumber=10
+T 200 3250 5 8 0 1 0 8 1
+pinseq=10
+T 350 3300 9 8 1 1 0 0 1
+pinlabel=RE2/_CS_/AN7
+T 350 3300 5 8 0 1 0 2 1
+pintype=io
+}
+P 0 3000 300 3000 1 0 0
+{
+T 200 3050 5 8 1 1 0 6 1
+pinnumber=11
+T 200 2950 5 8 0 1 0 8 1
+pinseq=11
+T 350 3000 9 8 1 1 0 0 1
+pinlabel=VDD
+T 350 3000 5 8 0 1 0 2 1
+pintype=pwr
+}
+P 0 2700 300 2700 1 0 0
+{
+T 200 2750 5 8 1 1 0 6 1
+pinnumber=12
+T 200 2650 5 8 0 1 0 8 1
+pinseq=12
+T 350 2700 9 8 1 1 0 0 1
+pinlabel=VSS
+T 350 2700 5 8 0 1 0 2 1
+pintype=pwr
+}
+P 0 2400 300 2400 1 0 0
+{
+T 200 2450 5 8 1 1 0 6 1
+pinnumber=13
+T 200 2350 5 8 0 1 0 8 1
+pinseq=13
+T 350 2400 9 8 1 1 0 0 1
+pinlabel=OSC1/CLKIN/RA7
+T 350 2400 5 8 0 1 0 2 1
+pintype=io
+}
+P 0 2100 300 2100 1 0 0
+{
+T 200 2150 5 8 1 1 0 6 1
+pinnumber=14
+T 200 2050 5 8 0 1 0 8 1
+pinseq=14
+T 350 2100 9 8 1 1 0 0 1
+pinlabel=OSC2/CLKOUT/RA6
+T 350 2100 5 8 0 1 0 2 1
+pintype=io
+}
+P 0 1800 300 1800 1 0 0
+{
+T 200 1850 5 8 1 1 0 6 1
+pinnumber=15
+T 200 1750 5 8 0 1 0 8 1
+pinseq=15
+T 350 1800 9 8 1 1 0 0 1
+pinlabel=RC0/T1OSO/T13CKI
+T 350 1800 5 8 0 1 0 2 1
+pintype=io
+}
+P 0 1500 300 1500 1 0 0
+{
+T 200 1550 5 8 1 1 0 6 1
+pinnumber=16
+T 200 1450 5 8 0 1 0 8 1
+pinseq=16
+T 350 1500 9 8 1 1 0 0 1
+pinlabel=RC1/T1OSI/CCP2
+T 350 1500 5 8 0 1 0 2 1
+pintype=io
+}
+P 0 1200 300 1200 1 0 0
+{
+T 200 1250 5 8 1 1 0 6 1
+pinnumber=17
+T 200 1150 5 8 0 1 0 8 1
+pinseq=17
+T 350 1200 9 8 1 1 0 0 1
+pinlabel=RC2/CCP1/P1A
+T 350 1200 5 8 0 1 0 2 1
+pintype=io
+}
+P 0 900 300 900 1 0 0
+{
+T 200 950 5 8 1 1 0 6 1
+pinnumber=18
+T 200 850 5 8 0 1 0 8 1
+pinseq=18
+T 350 900 9 8 1 1 0 0 1
+pinlabel=RC3/SCK/SCL
+T 350 900 5 8 0 1 0 2 1
+pintype=pwr
+}
+P 0 600 300 600 1 0 0
+{
+T 200 650 5 8 1 1 0 6 1
+pinnumber=19
+T 200 550 5 8 0 1 0 8 1
+pinseq=19
+T 350 600 9 8 1 1 0 0 1
+pinlabel=RD0/PSP0
+T 350 600 5 8 0 1 0 2 1
+pintype=io
+}
+P 0 300 300 300 1 0 0
+{
+T 200 350 5 8 1 1 0 6 1
+pinnumber=20
+T 200 250 5 8 0 1 0 8 1
+pinseq=20
+T 350 300 9 8 1 1 0 0 1
+pinlabel=RD1/PSP1
+T 350 300 5 8 0 1 0 2 1
+pintype=io
+}
+P 5400 6000 5100 6000 1 0 0
+{
+T 5200 6050 5 8 1 1 0 0 1
+pinnumber=40
+T 5200 5950 5 8 0 1 0 2 1
+pinseq=21
+T 5050 6000 9 8 1 1 0 6 1
+pinlabel=RB7/KBI3/PGD
+T 5050 6000 5 8 0 1 0 8 1
+pintype=io
+}
+P 5400 5700 5100 5700 1 0 0
+{
+T 5200 5750 5 8 1 1 0 0 1
+pinnumber=39
+T 5200 5650 5 8 0 1 0 2 1
+pinseq=22
+T 5050 5700 9 8 1 1 0 6 1
+pinlabel=RB6/KBI2/PGC
+T 5050 5700 5 8 0 1 0 8 1
+pintype=io
+}
+P 5400 5400 5100 5400 1 0 0
+{
+T 5200 5450 5 8 1 1 0 0 1
+pinnumber=38
+T 5200 5350 5 8 0 1 0 2 1
+pinseq=23
+T 5050 5400 9 8 1 1 0 6 1
+pinlabel=RB5/KBI1/PGM
+T 5050 5400 5 8 0 1 0 8 1
+pintype=io
+}
+P 5400 5100 5100 5100 1 0 0
+{
+T 5200 5150 5 8 1 1 0 0 1
+pinnumber=37
+T 5200 5050 5 8 0 1 0 2 1
+pinseq=24
+T 5050 5100 9 8 1 1 0 6 1
+pinlabel=RB4/KBI0/AN11/P1D
+T 5050 5100 5 8 0 1 0 8 1
+pintype=io
+}
+P 5400 4800 5100 4800 1 0 0
+{
+T 5200 4850 5 8 1 1 0 0 1
+pinnumber=36
+T 5200 4750 5 8 0 1 0 2 1
+pinseq=25
+T 5050 4800 9 8 1 1 0 6 1
+pinlabel=RB3/AN9/C12IN2-/CCP2
+T 5050 4800 5 8 0 1 0 8 1
+pintype=io
+}
+P 5400 4500 5100 4500 1 0 0
+{
+T 5200 4550 5 8 1 1 0 0 1
+pinnumber=35
+T 5200 4450 5 8 0 1 0 2 1
+pinseq=26
+T 5050 4500 9 8 1 1 0 6 1
+pinlabel=RB2/INT2/AN8
+T 5050 4500 5 8 0 1 0 8 1
+pintype=io
+}
+P 5400 4200 5100 4200 1 0 0
+{
+T 5200 4250 5 8 1 1 0 0 1
+pinnumber=34
+T 5200 4150 5 8 0 1 0 2 1
+pinseq=27
+T 5050 4200 9 8 1 1 0 6 1
+pinlabel=RB1/INT1/AN10/C12IN3-
+T 5050 4200 5 8 0 1 0 8 1
+pintype=io
+}
+P 5400 3900 5100 3900 1 0 0
+{
+T 5200 3950 5 8 1 1 0 0 1
+pinnumber=33
+T 5200 3850 5 8 0 1 0 2 1
+pinseq=28
+T 5050 3900 9 8 1 1 0 6 1
+pinlabel=RB0/INT0/FLT0/AN12
+T 5050 3900 5 8 0 1 0 8 1
+pintype=io
+}
+P 5400 3600 5100 3600 1 0 0
+{
+T 5200 3650 5 8 1 1 0 0 1
+pinnumber=32
+T 5200 3550 5 8 0 1 0 2 1
+pinseq=29
+T 5050 3600 9 8 1 1 0 6 1
+pinlabel=VDD
+T 5050 3600 5 8 0 1 0 8 1
+pintype=pwr
+}
+P 5400 3300 5100 3300 1 0 0
+{
+T 5200 3350 5 8 1 1 0 0 1
+pinnumber=31
+T 5200 3250 5 8 0 1 0 2 1
+pinseq=30
+T 5050 3300 9 8 1 1 0 6 1
+pinlabel=VSS
+T 5050 3300 5 8 0 1 0 8 1
+pintype=pwr
+}
+P 5400 3000 5100 3000 1 0 0
+{
+T 5200 3050 5 8 1 1 0 0 1
+pinnumber=30
+T 5200 2950 5 8 0 1 0 2 1
+pinseq=31
+T 5050 3000 9 8 1 1 0 6 1
+pinlabel=RD7/PSP7/P1D
+T 5050 3000 5 8 0 1 0 8 1
+pintype=io
+}
+P 5400 2700 5100 2700 1 0 0
+{
+T 5200 2750 5 8 1 1 0 0 1
+pinnumber=29
+T 5200 2650 5 8 0 1 0 2 1
+pinseq=32
+T 5050 2700 9 8 1 1 0 6 1
+pinlabel=RD6/PSP6/P1C
+T 5050 2700 5 8 0 1 0 8 1
+pintype=io
+}
+P 5400 2400 5100 2400 1 0 0
+{
+T 5200 2450 5 8 1 1 0 0 1
+pinnumber=28
+T 5200 2350 5 8 0 1 0 2 1
+pinseq=33
+T 5050 2400 9 8 1 1 0 6 1
+pinlabel=RD5/PSP5/P1B
+T 5050 2400 5 8 0 1 0 8 1
+pintype=io
+}
+P 5400 2100 5100 2100 1 0 0
+{
+T 5200 2150 5 8 1 1 0 0 1
+pinnumber=27
+T 5200 2050 5 8 0 1 0 2 1
+pinseq=34
+T 5050 2100 9 8 1 1 0 6 1
+pinlabel=RD4/PSP4
+T 5050 2100 5 8 0 1 0 8 1
+pintype=io
+}
+P 5400 1800 5100 1800 1 0 0
+{
+T 5200 1850 5 8 1 1 0 0 1
+pinnumber=26
+T 5200 1750 5 8 0 1 0 2 1
+pinseq=35
+T 5050 1800 9 8 1 1 0 6 1
+pinlabel=RC7/RX/DT
+T 5050 1800 5 8 0 1 0 8 1
+pintype=io
+}
+P 5400 1500 5100 1500 1 0 0
+{
+T 5200 1550 5 8 1 1 0 0 1
+pinnumber=25
+T 5200 1450 5 8 0 1 0 2 1
+pinseq=36
+T 5050 1500 9 8 1 1 0 6 1
+pinlabel=RC6/TX/CK
+T 5050 1500 5 8 0 1 0 8 1
+pintype=io
+}
+P 5400 1200 5100 1200 1 0 0
+{
+T 5200 1250 5 8 1 1 0 0 1
+pinnumber=24
+T 5200 1150 5 8 0 1 0 2 1
+pinseq=37
+T 5050 1200 9 8 1 1 0 6 1
+pinlabel=RC5/SDO
+T 5050 1200 5 8 0 1 0 8 1
+pintype=io
+}
+P 5400 900 5100 900 1 0 0
+{
+T 5200 950 5 8 1 1 0 0 1
+pinnumber=23
+T 5200 850 5 8 0 1 0 2 1
+pinseq=38
+T 5050 900 9 8 1 1 0 6 1
+pinlabel=RC4/SDI/SDA
+T 5050 900 5 8 0 1 0 8 1
+pintype=io
+}
+P 5400 600 5100 600 1 0 0
+{
+T 5200 650 5 8 1 1 0 0 1
+pinnumber=22
+T 5200 550 5 8 0 1 0 2 1
+pinseq=39
+T 5050 600 9 8 1 1 0 6 1
+pinlabel=RD3/PSP3
+T 5050 600 5 8 0 1 0 8 1
+pintype=io
+}
+P 5400 300 5100 300 1 0 0
+{
+T 5200 350 5 8 1 1 0 0 1
+pinnumber=21
+T 5200 250 5 8 0 1 0 2 1
+pinseq=40
+T 5050 300 9 8 1 1 0 6 1
+pinlabel=RD2/PSP2
+T 5050 300 5 8 0 1 0 8 1
+pintype=io
+}
+B 300 0 4800 6300 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
+T 5100 6400 8 10 1 1 0 6 1
+refdes=U?
+T 300 6400 9 10 1 0 0 0 1
+PIC18F46K20_DIP40
+T 300 6600 5 10 0 0 0 0 1
+device=PIC18F46K20_DIP40
+T 300 6800 5 10 0 0 0 0 1
+footprint=DIP40
+T 300 7000 5 10 0 0 0 0 1
+author=Kyuma Ohta <whatisthis.sowhat@gmail.com>
+T 300 7200 5 10 0 0 0 0 1
+documentation=http://ww1.microchip.com/downloads/en/DeviceDoc/41303G.pdf
+T 300 7400 5 10 0 0 0 0 1
+description=Microcontroller modified from PIC18F4550_DIP40 / PIC18F46K20_DIP40
+T 300 7600 5 10 0 0 0 0 1
+numslots=0
+T 300 7800 5 10 0 0 0 0 1
+dist-license=GPL
+T 300 8000 5 10 0 0 0 0 1
+use-license=public domain