{
tcg_gen_andi_i32(cpu_SR[sr], v,
dc->config->inttype_mask[INTTYPE_SOFTWARE]);
- gen_check_interrupts(dc);
}
static void gen_wsr_intclear(DisasContext *dc, uint32_t sr, TCGv_i32 v)
dc->config->inttype_mask[INTTYPE_SOFTWARE]);
tcg_gen_andc_i32(cpu_SR[INTSET], cpu_SR[INTSET], tmp);
tcg_temp_free(tmp);
- gen_check_interrupts(dc);
}
static void gen_wsr_intenable(DisasContext *dc, uint32_t sr, TCGv_i32 v)
{
tcg_gen_mov_i32(cpu_SR[sr], v);
- gen_check_interrupts(dc);
}
static void gen_wsr_ps(DisasContext *dc, uint32_t sr, TCGv_i32 v)
mask |= PS_RING;
}
tcg_gen_andi_i32(cpu_SR[sr], v, mask);
- gen_check_interrupts(dc);
}
static void gen_wsr_ccount(DisasContext *dc, uint32_t sr, TCGv_i32 v)
}
if (dc->base.is_jmp == DISAS_NEXT) {
+ if (op_flags & XTENSA_OP_CHECK_INTERRUPTS) {
+ gen_check_interrupts(dc);
+ }
+
if (op_flags & XTENSA_OP_EXIT_TB_M1) {
/* Change in mmu index, memory mapping or tb->flags; exit tb */
gen_jumpi_check_loop_end(dc, -1);
const uint32_t par[])
{
tcg_gen_andi_i32(cpu_SR[PS], cpu_SR[PS], ~PS_EXCM);
- gen_check_interrupts(dc);
gen_jump(dc, cpu_SR[EPC1]);
}
const uint32_t par[])
{
tcg_gen_mov_i32(cpu_SR[PS], cpu_SR[EPS2 + arg[0] - 2]);
- gen_check_interrupts(dc);
gen_jump(dc, cpu_SR[EPC1 + arg[0] - 1]);
}
cpu_SR[WINDOW_START], tmp);
}
+ tcg_temp_free(tmp);
gen_helper_restore_owb(cpu_env);
- gen_check_interrupts(dc);
gen_jump(dc, cpu_SR[EPC1]);
-
- tcg_temp_free(tmp);
}
static void translate_rotw(DisasContext *dc, const uint32_t arg[],
tcg_gen_mov_i32(cpu_R[arg[0]], cpu_SR[PS]);
tcg_gen_andi_i32(cpu_SR[PS], cpu_SR[PS], ~PS_INTLEVEL);
tcg_gen_ori_i32(cpu_SR[PS], cpu_SR[PS], arg[1]);
- gen_check_interrupts(dc);
}
static bool test_ill_rsr(DisasContext *dc, const uint32_t arg[],
}, {
.name = "rfe",
.translate = translate_rfe,
- .op_flags = XTENSA_OP_PRIVILEGED,
+ .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_CHECK_INTERRUPTS,
}, {
.name = "rfi",
.translate = translate_rfi,
- .op_flags = XTENSA_OP_PRIVILEGED,
+ .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_CHECK_INTERRUPTS,
}, {
.name = "rfwo",
.translate = translate_rfw,
.par = (const uint32_t[]){true},
- .op_flags = XTENSA_OP_PRIVILEGED,
+ .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_CHECK_INTERRUPTS,
}, {
.name = "rfwu",
.translate = translate_rfw,
.par = (const uint32_t[]){false},
- .op_flags = XTENSA_OP_PRIVILEGED,
+ .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_CHECK_INTERRUPTS,
}, {
.name = "ritlb0",
.translate = translate_rtlb,
}, {
.name = "rsil",
.translate = translate_rsil,
- .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_0,
+ .op_flags =
+ XTENSA_OP_PRIVILEGED |
+ XTENSA_OP_EXIT_TB_0 |
+ XTENSA_OP_CHECK_INTERRUPTS,
.windowed_register_op = 0x1,
}, {
.name = "rsr.176",
.translate = translate_wsr,
.test_ill = test_ill_wsr,
.par = (const uint32_t[]){INTCLEAR},
- .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_0,
+ .op_flags =
+ XTENSA_OP_PRIVILEGED |
+ XTENSA_OP_EXIT_TB_0 |
+ XTENSA_OP_CHECK_INTERRUPTS,
.windowed_register_op = 0x1,
}, {
.name = "wsr.intenable",
.translate = translate_wsr,
.test_ill = test_ill_wsr,
.par = (const uint32_t[]){INTENABLE},
- .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_0,
+ .op_flags =
+ XTENSA_OP_PRIVILEGED |
+ XTENSA_OP_EXIT_TB_0 |
+ XTENSA_OP_CHECK_INTERRUPTS,
.windowed_register_op = 0x1,
}, {
.name = "wsr.interrupt",
.translate = translate_wsr,
.test_ill = test_ill_wsr,
.par = (const uint32_t[]){INTSET},
- .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_0,
+ .op_flags =
+ XTENSA_OP_PRIVILEGED |
+ XTENSA_OP_EXIT_TB_0 |
+ XTENSA_OP_CHECK_INTERRUPTS,
.windowed_register_op = 0x1,
}, {
.name = "wsr.intset",
.translate = translate_wsr,
.test_ill = test_ill_wsr,
.par = (const uint32_t[]){INTSET},
- .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_0,
+ .op_flags =
+ XTENSA_OP_PRIVILEGED |
+ XTENSA_OP_EXIT_TB_0 |
+ XTENSA_OP_CHECK_INTERRUPTS,
.windowed_register_op = 0x1,
}, {
.name = "wsr.itlbcfg",
.translate = translate_wsr,
.test_ill = test_ill_wsr,
.par = (const uint32_t[]){PS},
- .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_M1,
+ .op_flags =
+ XTENSA_OP_PRIVILEGED |
+ XTENSA_OP_EXIT_TB_M1 |
+ XTENSA_OP_CHECK_INTERRUPTS,
.windowed_register_op = 0x1,
}, {
.name = "wsr.ptevaddr",
.translate = translate_xsr,
.test_ill = test_ill_xsr,
.par = (const uint32_t[]){INTCLEAR},
- .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_0,
+ .op_flags =
+ XTENSA_OP_PRIVILEGED |
+ XTENSA_OP_EXIT_TB_0 |
+ XTENSA_OP_CHECK_INTERRUPTS,
.windowed_register_op = 0x1,
}, {
.name = "xsr.intenable",
.translate = translate_xsr,
.test_ill = test_ill_xsr,
.par = (const uint32_t[]){INTENABLE},
- .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_0,
+ .op_flags =
+ XTENSA_OP_PRIVILEGED |
+ XTENSA_OP_EXIT_TB_0 |
+ XTENSA_OP_CHECK_INTERRUPTS,
.windowed_register_op = 0x1,
}, {
.name = "xsr.interrupt",
.translate = translate_xsr,
.test_ill = test_ill_xsr,
.par = (const uint32_t[]){INTSET},
- .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_0,
+ .op_flags =
+ XTENSA_OP_PRIVILEGED |
+ XTENSA_OP_EXIT_TB_0 |
+ XTENSA_OP_CHECK_INTERRUPTS,
.windowed_register_op = 0x1,
}, {
.name = "xsr.intset",
.translate = translate_xsr,
.test_ill = test_ill_xsr,
.par = (const uint32_t[]){INTSET},
- .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_0,
+ .op_flags =
+ XTENSA_OP_PRIVILEGED |
+ XTENSA_OP_EXIT_TB_0 |
+ XTENSA_OP_CHECK_INTERRUPTS,
.windowed_register_op = 0x1,
}, {
.name = "xsr.itlbcfg",
.translate = translate_xsr,
.test_ill = test_ill_xsr,
.par = (const uint32_t[]){PS},
- .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_M1,
+ .op_flags =
+ XTENSA_OP_PRIVILEGED |
+ XTENSA_OP_EXIT_TB_M1 |
+ XTENSA_OP_CHECK_INTERRUPTS,
.windowed_register_op = 0x1,
}, {
.name = "xsr.ptevaddr",