cpu and ppu integrated on main board.

diff --git a/simulation/address_decoder.vhd b/simulation/address_decoder.vhd
index 951a808..1bbf980 100644 (file)
--- a/simulation/address_decoder.vhd
+++ b/simulation/address_decoder.vhd
@@ -7,7 +7,8 @@ generic (abus_size : integer := 16; dbus_size : integer := 8);
     port (  phi2        : in std_logic; --dropping edge syncronized clock.
             R_nW        : in std_logic; -- active high on read / active low on write.
             addr        : in std_logic_vector (abus_size - 1 downto 0);
-            d_io        : inout std_logic_vector (dbus_size - 1 downto 0)
+            d_io        : inout std_logic_vector (dbus_size - 1 downto 0);
+            ppu_ce_n    : out std_logic
         );
 end address_decoder;
 
@@ -53,8 +54,6 @@ architecture rtl of address_decoder is
     signal apu_ce_n : std_logic;
     signal apu_io : std_logic_vector (dsize - 1 downto 0);
 
-    signal ppu_ce_n : std_logic;
-    signal ppu_io : std_logic_vector (dsize - 1 downto 0);
 begin
 
     rom_ce_n <= '0' when (addr(15) = '1' and R_nW = '1') else
@@ -72,14 +71,10 @@ begin
 
     ---dummy value.
     apu_io <= "00000000";
-    ppu_io <= "10000001";
 
     --must explicitly drive to for inout port.
     d_io <= ram_io 
             when (((addr(15) or addr(14) or addr(13)) = '0') and r_nw = '1')  else
-        ppu_io 
-            when ((addr(15) = '0') and  (addr(14) = '0') and  addr(13) = '1' 
-                        and  r_nw = '1')  else
         apu_io 
             when ((addr(15) = '0') and  (addr(14) = '1') and  addr(13) = '0' 
                         and  r_nw = '1')  else
@@ -88,6 +83,10 @@ begin
         (others => 'Z');
 
 
+    ppu_ce_n <= '0'
+            when (addr(15) = '0' and addr(14) = '0' and addr(13) = '1')  else
+                '1';
+
     --ram io timing.
     main_p : process (phi2, addr, d_io, R_nW)
     begin

diff --git a/simulation/cpu/testbench_mos6502.vhd b/simulation/cpu/testbench_mos6502.vhd
index 136eb9d..3172bab 100644 (file)
--- a/simulation/cpu/testbench_mos6502.vhd
+++ b/simulation/cpu/testbench_mos6502.vhd
@@ -31,7 +31,8 @@ architecture stimulus of testbench_mos6502 is
         port (  phi2        : in std_logic;
                 R_nW        : in std_logic; 
                 addr       : in std_logic_vector (abus_size - 1 downto 0);
-                d_io       : inout std_logic_vector (dbus_size - 1 downto 0)
+                d_io       : inout std_logic_vector (dbus_size - 1 downto 0);
+                ppu_ce_n    : out std_logic
     );
     end component;
 
@@ -43,6 +44,7 @@ architecture stimulus of testbench_mos6502 is
     signal rdy, rst_n, irq_n, nmi_n, dbe, r_nw, phi1, phi2 : std_logic;
     signal addr : std_logic_vector( asize - 1 downto 0);
     signal cpu_d : std_logic_vector( dsize - 1 downto 0);
+    signal ppu_ce_n    : std_logic;
 
 begin
 
@@ -53,8 +55,8 @@ begin
         port map (phi0, rdy, rst_n, irq_n, nmi_n, dbe, r_nw, 
                 phi1, phi2, addr, cpu_d);
 
-    addr_dec_inst : address_decoder generic map (asize, dsize) 
-        port map (phi2, r_nw, addr, cpu_d);
+--    addr_dec_inst : address_decoder generic map (asize, dsize) 
+--        port map (phi2, r_nw, addr, cpu_d, ppu_ce_n);
 
     reset_p : process
     begin

diff --git a/simulation/motones_sim.vhd b/simulation/motones_sim.vhd
index a534c77..5724afd 100644 (file)
--- a/simulation/motones_sim.vhd
+++ b/simulation/motones_sim.vhd
@@ -8,7 +8,7 @@ use ieee.std_logic_unsigned.conv_integer;
 --  
 
 entity motones_sim is 
-    port (  reset_n     : in std_logic
+    port (  rst_n     : in std_logic
          );
 end motones_sim;
 
@@ -44,36 +44,88 @@ architecture rtl of motones_sim is
         port (  phi2        : in std_logic;
                 R_nW        : in std_logic; 
                 addr       : in std_logic_vector (abus_size - 1 downto 0);
-                d_in       : in std_logic_vector (dbus_size - 1 downto 0);
-                d_out      : out std_logic_vector (dbus_size - 1 downto 0)
+                d_io       : inout std_logic_vector (dbus_size - 1 downto 0);
+                ppu_ce_n    : out std_logic
     );
     end component;
 
-    ---clock frequency = 21,477,270 (21 MHz)
-    constant base_clock_time : time := 46 ns;
+    component ppu
+    port (  clk         : in std_logic;
+            ce_n        : in std_logic;
+            rst_n       : in std_logic;
+            r_nw        : in std_logic;
+            cpu_addr    : in std_logic_vector (2 downto 0);
+            cpu_d       : inout std_logic_vector (7 downto 0);
+            vblank_n    : out std_logic;
+            rd_n        : out std_logic;
+            wr_n        : out std_logic;
+            ale         : out std_logic;
+            vram_ad     : inout std_logic_vector (7 downto 0);
+            vram_a      : out std_logic_vector (13 downto 8);
+            vga_clk     : in std_logic;
+            h_sync_n    : out std_logic;
+            v_sync_n    : out std_logic;
+            r           : out std_logic_vector(3 downto 0);
+            g           : out std_logic_vector(3 downto 0);
+            b           : out std_logic_vector(3 downto 0)
+    );
+    end component;
 
-    signal base_clk : std_logic;
-    signal cpu_clk, ppu_clk : std_logic;
+    component v_address_decoder
+    generic (abus_size : integer := 14; dbus_size : integer := 8);
+        port (  clk         : in std_logic; 
+                rd_n        : in std_logic;
+                wr_n        : in std_logic;
+                ale         : in std_logic;
+                vram_ad     : inout std_logic_vector (7 downto 0);
+                vram_a      : in std_logic_vector (13 downto 8)
+            );
+    end component;
 
+    component vga_device
+    port (  vga_clk     : in std_logic;
+            rst_n       : in std_logic;
+            h_sync_n    : in std_logic;
+            v_sync_n    : in std_logic;
+            r           : in std_logic_vector(3 downto 0);
+            g           : in std_logic_vector(3 downto 0);
+            b           : in std_logic_vector(3 downto 0)
+            );
+    end component;
+
+    ---clock frequency = 21,477,270 (21 MHz)
+    constant base_clock_time : time := 46 ns;
     constant data_size : integer := 8;
     constant addr_size : integer := 16;
+    constant size14    : integer := 14;
+
+    signal base_clk : std_logic;
+    signal cpu_clk  : std_logic;
+    signal ppu_clk  : std_logic;
 
     signal rdy, irq_n, nmi_n, dbe, r_nw : std_logic;
     signal phi1, phi2 : std_logic;
     signal addr : std_logic_vector( addr_size - 1 downto 0);
     signal d_io : std_logic_vector( data_size - 1 downto 0);
 
-begin
+    signal ppu_ce_n : std_logic;
+    signal rd_n     : std_logic;
+    signal wr_n     : std_logic;
+    signal ale      : std_logic;
+    signal vram_ad  : std_logic_vector (7 downto 0);
+    signal vram_a   : std_logic_vector (13 downto 8);
 
-    clock_inst : clock_divider port map 
-        (base_clk, reset_n, cpu_clk, ppu_clk);
+    signal vga_clk     : std_logic;
+    signal h_sync_n    : std_logic;
+    signal v_sync_n    : std_logic;
+    signal r           : std_logic_vector(3 downto 0);
+    signal g           : std_logic_vector(3 downto 0);
+    signal b           : std_logic_vector(3 downto 0);
 
-    cpu_inst : mos6502 generic map (data_size, addr_size) 
-        port map (cpu_clk, rdy, reset_n, irq_n, nmi_n, dbe, r_nw, 
-                phi1, phi2, addr, d_io);
+begin
 
---    addr_dec_inst : address_decoder generic map (addr_size, data_size) 
---        port map (phi2, r_nw, addr, d_out, d_in);
+    irq_n <= '0';
+    rdy <= '1';
 
     --- generate base clock.
     clock_p: process
@@ -84,6 +136,29 @@ begin
         wait for base_clock_time / 2;
     end process;
 
+    --ppu/cpu clock generator
+    clock_inst : clock_divider port map 
+        (base_clk, rst_n, cpu_clk, ppu_clk);
+
+    --mos 6502 cpu instance
+    cpu_inst : mos6502 generic map (data_size, addr_size) 
+        port map (cpu_clk, rdy, rst_n, irq_n, nmi_n, dbe, r_nw, 
+                phi1, phi2, addr, d_io);
+
+    addr_dec_inst : address_decoder generic map (addr_size, data_size) 
+        port map (phi2, r_nw, addr, d_io, ppu_ce_n);
+
+    --nes ppu instance
+    ppu_inst : ppu 
+        port map (ppu_clk, ppu_ce_n, rst_n, r_nw, addr(2 downto 0), d_io, 
+                nmi_n, rd_n, wr_n, ale, vram_ad, vram_a,
+                vga_clk, h_sync_n, v_sync_n, r, g, b);
+
+    ppu_addr_decoder : v_address_decoder generic map (size14, data_size) 
+        port map (ppu_clk, rd_n, wr_n, ale, vram_ad, vram_a);
+
+    dummy_vga_disp : vga_device 
+        port map (vga_clk, rst_n, h_sync_n, v_sync_n, r, g, b);
 
 end rtl;
 

diff --git a/simulation/ppu/testbench_ppu.vhd b/simulation/ppu/testbench_ppu.vhd
index fe30b51..3320d71 100644 (file)
--- a/simulation/ppu/testbench_ppu.vhd
+++ b/simulation/ppu/testbench_ppu.vhd
@@ -84,8 +84,6 @@ signal ale      : std_logic;
 signal vram_ad  : std_logic_vector (7 downto 0);
 signal vram_a   : std_logic_vector (13 downto 8);
 
-signal set_addr  : std_logic_vector (15 downto 0);
-
 signal vga_clk     : std_logic;
 signal h_sync_n    : std_logic;
 signal v_sync_n    : std_logic;

diff --git a/simulation/testbench_motones_sim.vhd b/simulation/testbench_motones_sim.vhd
index aeccc53..64385d8 100644 (file)
--- a/simulation/testbench_motones_sim.vhd
+++ b/simulation/testbench_motones_sim.vhd
@@ -9,21 +9,23 @@ end testbench_motones_sim;
 
 architecture stimulus of testbench_motones_sim is 
     component motones_sim
-        port (  reset_n     : in std_logic
+        port (  rst_n     : in std_logic
              );
     end component;
+
     signal reset_input : std_logic;
-    constant reset_time : time := 5000 ns;
+    constant powerup_time : time := 5000 ns;
+    constant reset_time : time := 500 ns;
 begin
 
     sim_board : motones_sim port map (reset_input);
     --- input reset.
     reset_p: process
     begin
-        wait for reset_time;
+        wait for powerup_time;
         reset_input <= '0';
 
-        wait for 100 ns;
+        wait for reset_time;
         reset_input <= '1';
 
         wait;