drm/i915/icl: Enable WaProgramMgsrForCorrectSliceSpecificMmioReads

WaProgramMgsrForCorrectSliceSpecificMmioReads applies for Icelake as
well.

References: HSD#1405586840, BSID#0575

v2:
 - GEN11 mask is different from its predecessors. (Oscar)
 - Better separate GEN10 and GEN11. (Oscar)

Cc: Oscar Mateo <oscar.mateo@intel.com>
Cc: Michel Thierry <michel.thierry@intel.com>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
Signed-off-by: Yunwei Zhang <yunwei.zhang@intel.com>
Reviewed-by: Oscar Mateo <oscar.mateo@intel.com>
Signed-off-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/1526683232-24753-1-git-send-email-yunwei.zhang@intel.com

diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c
index ad28680..13448ea 100644 (file)
--- a/drivers/gpu/drm/i915/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/intel_engine_cs.c
@@ -829,6 +829,9 @@ u32 intel_calculate_mcr_s_ss_select(struct drm_i915_private *dev_priv)
        if (INTEL_GEN(dev_priv) == 10)
                mcr_s_ss_select = GEN8_MCR_SLICE(slice) |
                                  GEN8_MCR_SUBSLICE(subslice);
+       else if (INTEL_GEN(dev_priv) >= 11)
+               mcr_s_ss_select = GEN11_MCR_SLICE(slice) |
+                                 GEN11_MCR_SUBSLICE(subslice);
        else
                mcr_s_ss_select = 0;
 

diff --git a/drivers/gpu/drm/i915/intel_workarounds.c b/drivers/gpu/drm/i915/intel_workarounds.c
index 720d863..2deec58 100644 (file)
--- a/drivers/gpu/drm/i915/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/intel_workarounds.c
@@ -679,10 +679,14 @@ static void wa_init_mcr(struct drm_i915_private *dev_priv)
 
        mcr = I915_READ(GEN8_MCR_SELECTOR);
 
-       mcr_slice_subslice_mask = GEN8_MCR_SLICE_MASK |
-                                 GEN8_MCR_SUBSLICE_MASK;
+       if (INTEL_GEN(dev_priv) >= 11)
+               mcr_slice_subslice_mask = GEN11_MCR_SLICE_MASK |
+                                         GEN11_MCR_SUBSLICE_MASK;
+       else
+               mcr_slice_subslice_mask = GEN8_MCR_SLICE_MASK |
+                                         GEN8_MCR_SUBSLICE_MASK;
        /*
-        * WaProgramMgsrForCorrectSliceSpecificMmioReads:cnl
+        * WaProgramMgsrForCorrectSliceSpecificMmioReads:cnl,icl
         * Before any MMIO read into slice/subslice specific registers, MCR
         * packet control register needs to be programmed to point to any
         * enabled s/ss pair. Otherwise, incorrect values will be returned.
@@ -719,6 +723,8 @@ static void cnl_gt_workarounds_apply(struct drm_i915_private *dev_priv)
 
 static void icl_gt_workarounds_apply(struct drm_i915_private *dev_priv)
 {
+       wa_init_mcr(dev_priv);
+
        /* This is not an Wa. Enable for better image quality */
        I915_WRITE(_3D_CHICKEN3,
                   _MASKED_BIT_ENABLE(_3D_CHICKEN3_AA_LINE_QUALITY_FIX_ENABLE));