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[X86] Remove an unnecessary alignment restriction from MOVDDUP pattern.
author
Craig Topper
<craig.topper@intel.com>
Sat, 19 Aug 2017 18:02:28 +0000
(18:02 +0000)
committer
Craig Topper
<craig.topper@intel.com>
Sat, 19 Aug 2017 18:02:28 +0000
(18:02 +0000)
The SSE MOVDDUP instruction only loads 64-bits with no alignment restriction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311253
91177308
-0d34-0410-b5e6-
96231b3b80d8
lib/Target/X86/X86InstrSSE.td
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diff --git
a/lib/Target/X86/X86InstrSSE.td
b/lib/Target/X86/X86InstrSSE.td
index
6ac7ae6
..
f5bc312
100644
(file)
--- a/
lib/Target/X86/X86InstrSSE.td
+++ b/
lib/Target/X86/X86InstrSSE.td
@@
-5048,7
+5048,8
@@
def : Pat<(v2i64 (X86VBroadcast (loadi64 addr:$src))),
(VMOVDDUPrm addr:$src)>;
let Predicates = [UseSSE3] in {
- def : Pat<(X86Movddup (memopv2f64 addr:$src)),
+ // No need for aligned memory as this only loads 64-bits.
+ def : Pat<(X86Movddup (loadv2f64 addr:$src)),
(MOVDDUPrm addr:$src)>;
}