ARM: dts: mmp3: Add the GPU

There's a GC2000 3D core accompanied by a GC300 2D core.

Link: https://lore.kernel.org/r/20200718205019.184927-13-lkundrak@v3.sk
Signed-off-by: Lubomir Rintel <lkundrak@v3.sk>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>

diff --git a/arch/arm/boot/dts/mmp3.dtsi b/arch/arm/boot/dts/mmp3.dtsi
index 57231d4..cc4efd0 100644 (file)
--- a/arch/arm/boot/dts/mmp3.dtsi
+++ b/arch/arm/boot/dts/mmp3.dtsi
@@ -4,6 +4,7 @@
  */
 
 #include <dt-bindings/clock/marvell,mmp2.h>
+#include <dt-bindings/power/marvell,mmp2.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 
 / {
@@ -310,6 +311,30 @@
                                clock-output-names = "mclk";
                                status = "disabled";
                        };
+
+                       gpu_3d: gpu@d420d000 {
+                               compatible = "vivante,gc";
+                               reg = <0xd420d000 0x2000>;
+                               interrupt-parent = <&gpu_mux>;
+                               interrupts = <0>;
+                               status = "disabled";
+                               clocks = <&soc_clocks MMP3_CLK_GPU_3D>,
+                                        <&soc_clocks MMP3_CLK_GPU_BUS>;
+                               clock-names = "core", "bus";
+                               power-domains = <&soc_clocks MMP2_POWER_DOMAIN_GPU>;
+                       };
+
+                       gpu_2d: gpu@d420f000 {
+                               compatible = "vivante,gc";
+                               reg = <0xd420f000 0x2000>;
+                               interrupt-parent = <&gpu_mux>;
+                               interrupts = <2>;
+                               status = "disabled";
+                               clocks = <&soc_clocks MMP3_CLK_GPU_2D>,
+                                        <&soc_clocks MMP3_CLK_GPU_BUS>;
+                               clock-names = "core", "bus";
+                               power-domains = <&soc_clocks MMP2_POWER_DOMAIN_GPU>;
+                       };
                };
 
                apb@d4000000 {