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dsa: qca8k: add mac_power_sel support
authorAnsuel Smith <ansuelsmth@gmail.com>
Wed, 13 Oct 2021 22:39:06 +0000 (00:39 +0200)
committerDavid S. Miller <davem@davemloft.net>
Fri, 15 Oct 2021 10:06:37 +0000 (11:06 +0100)
Add missing mac power sel support needed for ipq8064/5 SoC that require
1.8v for the internal regulator port instead of the default 1.5v.
If other device needs this, consider adding a dedicated binding to
support this.

Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
Reviewed-by: Vladimir Oltean <olteanv@gmail.com>
Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
drivers/net/dsa/qca8k.c
drivers/net/dsa/qca8k.h

index a984f06..db97f45 100644 (file)
@@ -951,6 +951,33 @@ qca8k_setup_of_rgmii_delay(struct qca8k_priv *priv)
 }
 
 static int
+qca8k_setup_mac_pwr_sel(struct qca8k_priv *priv)
+{
+       u32 mask = 0;
+       int ret = 0;
+
+       /* SoC specific settings for ipq8064.
+        * If more device require this consider adding
+        * a dedicated binding.
+        */
+       if (of_machine_is_compatible("qcom,ipq8064"))
+               mask |= QCA8K_MAC_PWR_RGMII0_1_8V;
+
+       /* SoC specific settings for ipq8065 */
+       if (of_machine_is_compatible("qcom,ipq8065"))
+               mask |= QCA8K_MAC_PWR_RGMII1_1_8V;
+
+       if (mask) {
+               ret = qca8k_rmw(priv, QCA8K_REG_MAC_PWR_SEL,
+                               QCA8K_MAC_PWR_RGMII0_1_8V |
+                               QCA8K_MAC_PWR_RGMII1_1_8V,
+                               mask);
+       }
+
+       return ret;
+}
+
+static int
 qca8k_setup(struct dsa_switch *ds)
 {
        struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv;
@@ -979,6 +1006,10 @@ qca8k_setup(struct dsa_switch *ds)
        if (ret)
                return ret;
 
+       ret = qca8k_setup_mac_pwr_sel(priv);
+       if (ret)
+               return ret;
+
        /* Enable CPU Port */
        ret = qca8k_reg_set(priv, QCA8K_REG_GLOBAL_FW_CTRL0,
                            QCA8K_GLOBAL_FW_CTRL0_CPU_PORT_EN);
index ed3b05a..fc7db94 100644 (file)
 #define   QCA8K_SGMII_MODE_CTRL_PHY                    (1 << 22)
 #define   QCA8K_SGMII_MODE_CTRL_MAC                    (2 << 22)
 
+/* MAC_PWR_SEL registers */
+#define QCA8K_REG_MAC_PWR_SEL                          0x0e4
+#define   QCA8K_MAC_PWR_RGMII1_1_8V                    BIT(18)
+#define   QCA8K_MAC_PWR_RGMII0_1_8V                    BIT(19)
+
 /* EEE control registers */
 #define QCA8K_REG_EEE_CTRL                             0x100
 #define  QCA8K_REG_EEE_CTRL_LPI_EN(_i)                 ((_i + 1) * 2)