/*\r
- Produced by NSL Core(version=20110302), IP ARCH, Inc. Fri Nov 04 16:26:51 2011\r
+ Produced by NSL Core(version=20110302), IP ARCH, Inc. Sun Nov 06 15:57:59 2011\r
Licensed to Yujiro_Kaneko::yujiro.kaneko@overtone.co.jp :NON PROFIT USER:\r
*/\r
+\r
+module vga_gen ( i_clk50 , i_fifo_rst , m_clock , p_reset , o_vsync , o_hsync , o_vga_r , o_vga_g , o_vga_b , o_dummy_rgb , o_vcnt , i_wrdata , fi_fifo_write , o_rdack , o_led );\r
+ input i_clk50;\r
+ input i_fifo_rst;\r
+ input m_clock;\r
+ input p_reset;\r
+ output o_vsync;\r
+ output o_hsync;\r
+ output [3:0] o_vga_r;\r
+ output [3:0] o_vga_g;\r
+ output [3:0] o_vga_b;\r
+ output [2:0] o_dummy_rgb;\r
+ output [9:0] o_vcnt;\r
+ input [7:0] i_wrdata;\r
+ input fi_fifo_write;\r
+ output o_rdack;\r
+ output o_led;\r
+ wire fs_fifo_read;\r
+ wire [7:0] w_rddata;\r
+ wire fs_fifo_ack;\r
+ wire fs_initialize;\r
+ reg [7:0] r_data1;\r
+ reg [7:0] r_data2;\r
+ reg r_reg_cnt;\r
+ reg [2:0] r_bit_cnt;\r
+ reg r_vsync;\r
+ reg r_hsync;\r
+ reg [9:0] r_vcnt;\r
+ reg [9:0] r_hcnt;\r
+ reg [25:0] r_cnt;\r
+ reg [2:0] r_outcnt;\r
+ reg [6:0] r_outclr;\r
+ reg r_vcnt_hld;\r
+ reg r_led;\r
+ reg r_init_flg;\r
+ reg [2:0] r_trg;\r
+ wire _u_FIFO_i_rst;\r
+ wire _u_FIFO_i_clk50;\r
+ wire _u_FIFO_i_clk25;\r
+ wire _u_FIFO_i_we;\r
+ wire [7:0] _u_FIFO_i_wrdata;\r
+ wire _u_FIFO_i_re;\r
+ wire [7:0] _u_FIFO_o_rddata;\r
+ wire _u_FIFO_o_rdack;\r
+ wire _net_0;\r
+ wire _net_1;\r
+ wire _net_2;\r
+ wire _net_3;\r
+ wire _net_4;\r
+ wire _net_5;\r
+ wire _net_6;\r
+ wire _net_7;\r
+ wire _net_8;\r
+ wire _net_9;\r
+ wire _net_10;\r
+ wire _net_11;\r
+ wire _net_12;\r
+ wire _net_13;\r
+ wire _net_14;\r
+ wire _net_15;\r
+ wire _net_16;\r
+ wire _net_17;\r
+ wire _net_18;\r
+ wire _net_19;\r
+ wire _net_20;\r
+ wire _net_21;\r
+ wire _net_22;\r
+ wire _net_23;\r
+ wire _net_24;\r
+ wire _net_25;\r
+ wire _net_26;\r
+ wire _net_27;\r
+ wire _net_28;\r
+ wire _net_29;\r
+ wire _net_30;\r
+ wire _net_31;\r
+ wire _net_32;\r
+ wire _net_33;\r
+ wire _net_34;\r
+ wire _net_35;\r
+ wire _net_36;\r
+ wire _net_37;\r
+ wire _net_38;\r
+ wire _net_39;\r
+ wire _net_40;\r
+ wire _net_41;\r
+ wire _net_42;\r
+ wire _net_43;\r
+ wire _net_44;\r
+ wire _net_45;\r
+ wire _net_46;\r
+ wire _net_47;\r
+ wire _net_48;\r
+ wire _net_49;\r
+ wire _net_50;\r
+ wire _net_51;\r
+ wire _net_52;\r
+ wire _net_53;\r
+ reg _reg_54;\r
+ reg _reg_55;\r
+ reg _reg_56;\r
+ reg _reg_57;\r
+ reg _reg_58;\r
+ wire _net_59;\r
+ wire _net_60;\r
+ wire _net_61;\r
+ wire _net_62;\r
+ wire _net_63;\r
+ reg _reg_64;\r
+ reg _reg_65;\r
+ wire _net_66;\r
+vga_ram u_FIFO (.o_rdack(_u_FIFO_o_rdack), .o_rddata(_u_FIFO_o_rddata), .i_re(_u_FIFO_i_re), .i_wrdata(_u_FIFO_i_wrdata), .i_we(_u_FIFO_i_we), .i_clk25(_u_FIFO_i_clk25), .i_clk50(_u_FIFO_i_clk50), .i_rst(_u_FIFO_i_rst));\r
+\r
+ assign fs_fifo_read = _net_59|_reg_56|_net_15;\r
+ assign w_rddata = _u_FIFO_o_rddata;\r
+ assign fs_fifo_ack = _reg_64;\r
+ assign fs_initialize = _net_0;\r
+ assign _u_FIFO_i_rst = i_fifo_rst;\r
+ assign _u_FIFO_i_clk50 = i_clk50;\r
+ assign _u_FIFO_i_clk25 = m_clock;\r
+ assign _u_FIFO_i_we = fi_fifo_write;\r
+ assign _u_FIFO_i_wrdata = i_wrdata;\r
+ assign _u_FIFO_i_re = fs_fifo_read;\r
+ assign _net_0 = (r_trg)==(3'b011);\r
+ assign _net_1 = (r_cnt)==(26'b01011111010111100001000000);\r
+ assign _net_2 = ~_net_1;\r
+ assign _net_3 = (r_hcnt) < (10'b1100100000);\r
+ assign _net_4 = r_init_flg&_net_3;\r
+ assign _net_5 = r_init_flg&(~_net_3);\r
+ assign _net_6 = (r_vcnt) < (10'b1000001001);\r
+ assign _net_7 = r_init_flg&(~_net_3);\r
+ assign _net_8 = (r_init_flg&(~_net_3))&_net_6;\r
+ assign _net_9 = (r_init_flg&(~_net_3))&(~_net_6);\r
+ assign _net_10 = ((r_hcnt) < (10'b1010000000))&((r_vcnt) < (10'b0111100000));\r
+ assign _net_11 = _net_10&r_init_flg;\r
+ assign _net_12 = (r_bit_cnt)==(3'b111);\r
+ assign _net_13 = _net_10&r_init_flg;\r
+ assign _net_14 = (_net_10&r_init_flg)&_net_12;\r
+ assign _net_15 = (_net_10&r_init_flg)&_net_12;\r
+ assign _net_16 = ((_net_10&r_init_flg)&fs_fifo_ack)&r_reg_cnt;\r
+ assign _net_17 = ~r_reg_cnt;\r
+ assign _net_18 = (_net_10&r_init_flg)&fs_fifo_ack;\r
+ assign _net_19 = ((_net_10&r_init_flg)&fs_fifo_ack)&_net_17;\r
+ assign _net_20 = (r_reg_cnt)==(1'b0);\r
+ assign _net_21 = _net_10&r_init_flg;\r
+ assign _net_22 = (_net_10&r_init_flg)&_net_20;\r
+ assign _net_23 = (_net_10&r_init_flg)&(~_net_20);\r
+ assign _net_24 = (r_outcnt) < (3'b100);\r
+ assign _net_25 = _net_10&_net_24;\r
+ assign _net_26 = _net_10&(~_net_24);\r
+ assign _net_27 = _net_10&(~_net_24);\r
+ assign _net_28 = ~(r_outclr[4]);\r
+ assign _net_29 = _net_10&_net_28;\r
+ assign _net_30 = _net_10&(~_net_28);\r
+ assign _net_31 = ~(r_outclr[5]);\r
+ assign _net_32 = _net_10&_net_31;\r
+ assign _net_33 = _net_10&(~_net_31);\r
+ assign _net_34 = ~(r_outclr[6]);\r
+ assign _net_35 = _net_10&_net_34;\r
+ assign _net_36 = _net_10&(~_net_34);\r
+ assign _net_37 = (r_hcnt)==(10'b1011110000);\r
+ assign _net_38 = ~_net_10;\r
+ assign _net_39 = (~_net_10)&_net_37;\r
+ assign _net_40 = (r_hcnt)==(10'b1010010000);\r
+ assign _net_41 = ~_net_10;\r
+ assign _net_42 = (~_net_10)&_net_40;\r
+ assign _net_43 = (r_hcnt)==(10'b1010000000);\r
+ assign _net_44 = ~_net_10;\r
+ assign _net_45 = (~_net_10)&_net_43;\r
+ assign _net_46 = (~_net_10)&_net_43;\r
+ assign _net_47 = (~_net_10)&_net_43;\r
+ assign _net_48 = (~_net_10)&_net_43;\r
+ assign _net_49 = (~_net_10)&_net_43;\r
+ assign _net_50 = (~_net_10)&_net_43;\r
+ assign _net_51 = (r_vcnt)==(10'b0111101100);\r
+ assign _net_52 = (r_vcnt)==(10'b0111101010);\r
+ assign _net_53 = (r_vcnt)==(10'b0111100000);\r
+ assign _net_59 = fs_initialize|_reg_58;\r
+ assign _net_60 = fs_initialize|_reg_57|_reg_58;\r
+ assign _net_61 = fs_initialize|_reg_56|_reg_57;\r
+ assign _net_62 = fs_initialize|_reg_55|_reg_56;\r
+ assign _net_63 = fs_initialize|_reg_54|_reg_55;\r
+ assign _net_66 = fs_fifo_read|_reg_64|_reg_65;\r
+ assign o_vsync = r_vsync;\r
+ assign o_hsync = r_hsync;\r
+ assign o_vga_r = ((_net_45|_net_33)?4'b0000:4'b0)|\r
+ ((_net_32)?~(r_outclr[3:0]):4'b0);\r
+ assign o_vga_g = ((_net_46|_net_36)?4'b0000:4'b0)|\r
+ ((_net_35)?~(r_outclr[3:0]):4'b0);\r
+ assign o_vga_b = ((_net_47|_net_30)?4'b0000:4'b0)|\r
+ ((_net_29)?~(r_outclr[3:0]):4'b0);\r
+ assign o_dummy_rgb = ((_net_50)?3'b000:3'b0)|\r
+ ((_net_23)?{{2{r_data2[r_bit_cnt]}},r_data2[r_bit_cnt]}:3'b0)|\r
+ ((_net_22)?{{2{r_data1[r_bit_cnt]}},r_data1[r_bit_cnt]}:3'b0);\r
+ assign o_vcnt = r_vcnt;\r
+ assign o_rdack = _u_FIFO_o_rdack;\r
+ assign o_led = r_led;\r
+always @(posedge m_clock or posedge p_reset)\r
+ begin\r
+if (p_reset)\r
+ r_data1 <= 8'b00000000;\r
+else if ((_reg_57)|(_net_16)) \r
+ r_data1 <= ((_reg_57) ?_u_FIFO_o_rddata:8'b0)|\r
+ ((_net_16) ?w_rddata:8'b0);\r
+\r
+end\r
+always @(posedge m_clock or posedge p_reset)\r
+ begin\r
+if (p_reset)\r
+ r_data2 <= 8'b00000000;\r
+else if ((_reg_55)|(_net_19)) \r
+ r_data2 <= ((_reg_55) ?_u_FIFO_o_rddata:8'b0)|\r
+ ((_net_19) ?w_rddata:8'b0);\r
+\r
+end\r
+always @(posedge m_clock or posedge p_reset)\r
+ begin\r
+if (p_reset)\r
+ r_reg_cnt <= 1'b0;\r
+else if ((_net_14)) \r
+ r_reg_cnt <= ~r_reg_cnt;\r
+end\r
+always @(posedge m_clock or posedge p_reset)\r
+ begin\r
+if (p_reset)\r
+ r_bit_cnt <= 3'b000;\r
+else if ((_net_11)) \r
+ r_bit_cnt <= (r_bit_cnt)+(3'b001);\r
+end\r
+always @(posedge m_clock or posedge p_reset)\r
+ begin\r
+if (p_reset)\r
+ r_vsync <= 1'b0;\r
+else if ((_net_52)|(_net_51)) \r
+ r_vsync <= ((_net_52) ?1'b0:1'b0)|\r
+ ((_net_51) ?1'b1:1'b0);\r
+\r
+end\r
+always @(posedge m_clock or posedge p_reset)\r
+ begin\r
+if (p_reset)\r
+ r_hsync <= 1'b0;\r
+else if ((_net_42)|(_net_39)) \r
+ r_hsync <= ((_net_42) ?1'b0:1'b0)|\r
+ ((_net_39) ?1'b1:1'b0);\r
+\r
+end\r
+always @(posedge m_clock or posedge p_reset)\r
+ begin\r
+if (p_reset)\r
+ r_vcnt <= 10'b0000000000;\r
+else if ((_net_9)|(_net_8)) \r
+ r_vcnt <= ((_net_9) ?10'b0000000000:10'b0)|\r
+ ((_net_8) ?(r_vcnt)+(10'b0000000001):10'b0);\r
+\r
+end\r
+always @(posedge m_clock or posedge p_reset)\r
+ begin\r
+if (p_reset)\r
+ r_hcnt <= 10'b0000000000;\r
+else if ((_net_5)|(_net_4)) \r
+ r_hcnt <= ((_net_5) ?10'b0000000000:10'b0)|\r
+ ((_net_4) ?(r_hcnt)+(10'b0000000001):10'b0);\r
+\r
+end\r
+always @(posedge m_clock or posedge p_reset)\r
+ begin\r
+if (p_reset)\r
+ r_cnt <= 26'b00000000000000000000000000;\r
+else if ((_net_2)|(_net_1)) \r
+ r_cnt <= ((_net_2) ?(r_cnt)+(26'b00000000000000000000000001):26'b0)|\r
+ ((_net_1) ?26'b00000000000000000000000000:26'b0);\r
+\r
+end\r
+always @(posedge m_clock or posedge p_reset)\r
+ begin\r
+if (p_reset)\r
+ r_outcnt <= 3'b000;\r
+else if ((_net_48|_net_26)|(_net_25)) \r
+ r_outcnt <= ((_net_48|_net_26) ?3'b000:3'b0)|\r
+ ((_net_25) ?(r_outcnt)+(3'b001):3'b0);\r
+\r
+end\r
+always @(posedge m_clock or posedge p_reset)\r
+ begin\r
+if (p_reset)\r
+ r_outclr <= 7'b0000000;\r
+else if ((_net_49)|(_net_27)) \r
+ r_outclr <= ((_net_49) ?7'b0000000:7'b0)|\r
+ ((_net_27) ?(r_outclr)+(7'b0000001):7'b0);\r
+\r
+end\r
+always @(posedge p_reset)\r
+ begin\r
+if (p_reset)\r
+ r_vcnt_hld <= 1'b0;\r
+end\r
+always @(posedge m_clock or posedge p_reset)\r
+ begin\r
+if (p_reset)\r
+ r_led <= 1'b0;\r
+else if ((_net_1)) \r
+ r_led <= ~r_led;\r
+end\r
+always @(posedge m_clock or posedge p_reset)\r
+ begin\r
+if (p_reset)\r
+ r_init_flg <= 1'b0;\r
+else if ((_reg_54)) \r
+ r_init_flg <= 1'b1;\r
+end\r
+always @(posedge m_clock or posedge p_reset)\r
+ begin\r
+if (p_reset)\r
+ r_trg <= 3'b000;\r
+else r_trg <= {r_trg[1:0],1'b1};\r
+end\r
+always @(posedge m_clock or posedge p_reset)\r
+ begin\r
+if (p_reset)\r
+ _reg_54 <= 1'b0;\r
+else if ((_net_63)) \r
+ _reg_54 <= _reg_55;\r
+end\r
+always @(posedge m_clock or posedge p_reset)\r
+ begin\r
+if (p_reset)\r
+ _reg_55 <= 1'b0;\r
+else if ((_net_62)) \r
+ _reg_55 <= _reg_56;\r
+end\r
+always @(posedge m_clock or posedge p_reset)\r
+ begin\r
+if (p_reset)\r
+ _reg_56 <= 1'b0;\r
+else if ((_net_61)) \r
+ _reg_56 <= _reg_57;\r
+end\r
+always @(posedge m_clock or posedge p_reset)\r
+ begin\r
+if (p_reset)\r
+ _reg_57 <= 1'b0;\r
+else if ((_net_60)) \r
+ _reg_57 <= _reg_58|fs_initialize;\r
+end\r
+always @(posedge m_clock or posedge p_reset)\r
+ begin\r
+if (p_reset)\r
+ _reg_58 <= 1'b0;\r
+else if ((_reg_58)) \r
+ _reg_58 <= 1'b0;\r
+end\r
+always @(posedge m_clock or posedge p_reset)\r
+ begin\r
+if (p_reset)\r
+ _reg_64 <= 1'b0;\r
+else if ((_net_66)) \r
+ _reg_64 <= _reg_65|fs_fifo_read;\r
+end\r
+always @(posedge m_clock or posedge p_reset)\r
+ begin\r
+if (p_reset)\r
+ _reg_65 <= 1'b0;\r
+else if ((_reg_65)) \r
+ _reg_65 <= 1'b0;\r
+end\r
+endmodule\r
+/*\r
+ Produced by NSL Core(version=20110302), IP ARCH, Inc. Sun Nov 06 15:58:02 2011\r
+ Licensed to Yujiro_Kaneko::yujiro.kaneko@overtone.co.jp \r
+*/\r
/*\r
- Produced by NSL Core(version=20110302), IP ARCH, Inc. Wed Sep 21 22:07:53 2011\r
- Licensed to Yujiro_Kaneko::zyangalianhamster01@gmail.com :NON PROFIT USER:\r
+ Produced by NSL Core(version=20110302), IP ARCH, Inc. Sun Nov 06 16:37:27 2011\r
+ Licensed to Yujiro_Kaneko::yujiro.kaneko@overtone.co.jp :NON PROFIT USER:\r
*/\r
\r
-module vga_gen ( i_clk50M , m_clock , p_reset , o_vsync , o_hsync , o_vga_r , o_vga_g , o_vga_b , i_wrdata1 , i_wrdata2 , i_wradrs1 , i_wradrs2 , fi_fifo1_write , fi_fifo2_write , outled , o_vcnt );\r
- input i_clk50M;\r
+module vga_gen ( i_clk50 , i_fifo_rst , m_clock , p_reset , o_vsync , o_hsync , o_vga_r , o_vga_g , o_vga_b , o_dummy_rgb , o_vcnt , i_wrdata , fi_fifo_write , o_rdack , o_led );\r
+ input i_clk50;\r
+ input i_fifo_rst;\r
input m_clock;\r
input p_reset;\r
output o_vsync;\r
output [3:0] o_vga_r;\r
output [3:0] o_vga_g;\r
output [3:0] o_vga_b;\r
- input [7:0] i_wrdata1;\r
- input [7:0] i_wrdata2;\r
- input [7:0] i_wradrs1;\r
- input [7:0] i_wradrs2;\r
- input fi_fifo1_write;\r
- input fi_fifo2_write;\r
- output outled;\r
+ output [2:0] o_dummy_rgb;\r
output [9:0] o_vcnt;\r
- wire fs_fifo1_read;\r
- wire fs_fifo2_read;\r
- wire fs_fifo1_exec;\r
- wire fs_fifo2_exec;\r
- wire fs_fifo1_reset;\r
- wire fs_fifo2_reset;\r
- reg [4:0] r_bit_number;\r
+ input [7:0] i_wrdata;\r
+ input fi_fifo_write;\r
+ output o_rdack;\r
+ output o_led;\r
+ wire fs_fifo_read;\r
+ wire [7:0] w_rddata;\r
+ wire fs_fifo_ack;\r
+ wire fs_initialize;\r
+ reg [7:0] r_data1;\r
+ reg [7:0] r_data2;\r
+ reg r_reg_cnt;\r
+ reg [2:0] r_bit_cnt;\r
reg r_vsync;\r
reg r_hsync;\r
reg [9:0] r_vcnt;\r
reg [9:0] r_hcnt;\r
- reg [25:0] cnt;\r
- reg testled;\r
+ reg [25:0] r_cnt;\r
reg [2:0] r_outcnt;\r
reg [6:0] r_outclr;\r
reg r_vcnt_hld;\r
- wire [23:0] w_rddata1;\r
- wire [23:0] w_rddata2;\r
- reg [7:0] r_rdadrs1;\r
- reg [7:0] r_rdadrs2;\r
- wire _u_FIFO_p_reset;\r
- wire _u_FIFO_m_clock;\r
- wire _u_FIFO_i_we1;\r
- wire [7:0] _u_FIFO_i_wrdata1;\r
- wire [7:0] _u_FIFO_i_wradrs1;\r
- wire _u_FIFO_i_we2;\r
- wire [7:0] _u_FIFO_i_wrdata2;\r
- wire [7:0] _u_FIFO_i_wradrs2;\r
- wire [23:0] _u_FIFO_o_rddata1;\r
- wire [23:0] _u_FIFO_o_rddata2;\r
- wire [7:0] _u_FIFO_i_rdadrs1;\r
- wire [7:0] _u_FIFO_i_rdadrs2;\r
- wire _u_FIFO_i_clock;\r
- wire _u_FIFO_i_re1;\r
- wire _u_FIFO_i_re2;\r
- wire _u_FIFO_o_rdack1;\r
- wire _u_FIFO_o_rdack2;\r
+ reg r_led;\r
+ reg r_init_flg;\r
+ reg [2:0] r_trg;\r
+ wire _u_FIFO_i_rst;\r
+ wire _u_FIFO_i_clk50;\r
+ wire _u_FIFO_i_clk25;\r
+ wire _u_FIFO_i_we;\r
+ wire [7:0] _u_FIFO_i_wrdata;\r
+ wire _u_FIFO_i_re;\r
+ wire [7:0] _u_FIFO_o_rddata;\r
+ wire _u_FIFO_o_rdack;\r
wire _net_0;\r
wire _net_1;\r
wire _net_2;\r
wire _net_51;\r
wire _net_52;\r
wire _net_53;\r
- wire _net_54;\r
-vga_ram u_FIFO (.o_rdack2(_u_FIFO_o_rdack2), .o_rdack1(_u_FIFO_o_rdack1), .i_re2(_u_FIFO_i_re2), .i_re1(_u_FIFO_i_re1), .i_clock(_u_FIFO_i_clock), .i_rdadrs2(_u_FIFO_i_rdadrs2), .i_rdadrs1(_u_FIFO_i_rdadrs1), .o_rddata2(_u_FIFO_o_rddata2), .o_rddata1(_u_FIFO_o_rddata1), .i_wradrs2(_u_FIFO_i_wradrs2), .i_wrdata2(_u_FIFO_i_wrdata2), .i_we2(_u_FIFO_i_we2), .i_wradrs1(_u_FIFO_i_wradrs1), .i_wrdata1(_u_FIFO_i_wrdata1), .i_we1(_u_FIFO_i_we1), .m_clock(_u_FIFO_m_clock), .p_reset(_u_FIFO_p_reset));\r
+ reg _reg_54;\r
+ reg _reg_55;\r
+ reg _reg_56;\r
+ reg _reg_57;\r
+ reg _reg_58;\r
+ wire _net_59;\r
+ wire _net_60;\r
+ wire _net_61;\r
+ wire _net_62;\r
+ wire _net_63;\r
+ reg _reg_64;\r
+ reg _reg_65;\r
+ wire _net_66;\r
+vga_ram u_FIFO (.o_rdack(_u_FIFO_o_rdack), .o_rddata(_u_FIFO_o_rddata), .i_re(_u_FIFO_i_re), .i_wrdata(_u_FIFO_i_wrdata), .i_we(_u_FIFO_i_we), .i_clk25(_u_FIFO_i_clk25), .i_clk50(_u_FIFO_i_clk50), .i_rst(_u_FIFO_i_rst));\r
\r
- assign fs_fifo1_read = _net_22;\r
- assign fs_fifo2_read = _net_19;\r
- assign fs_fifo1_exec = _net_14;\r
- assign fs_fifo2_exec = _net_12;\r
- assign fs_fifo1_reset = _net_1;\r
- assign fs_fifo2_reset = _net_0;\r
- assign w_rddata1 = _u_FIFO_o_rddata1;\r
- assign w_rddata2 = _u_FIFO_o_rddata2;\r
- assign _u_FIFO_m_clock = m_clock;\r
- assign _u_FIFO_i_we1 = fi_fifo1_write;\r
- assign _u_FIFO_i_wrdata1 = i_wrdata1;\r
- assign _u_FIFO_i_wradrs1 = i_wradrs1;\r
- assign _u_FIFO_i_we2 = fi_fifo2_write;\r
- assign _u_FIFO_i_wrdata2 = i_wrdata2;\r
- assign _u_FIFO_i_wradrs2 = i_wradrs2;\r
- assign _u_FIFO_i_rdadrs1 = r_rdadrs1;\r
- assign _u_FIFO_i_rdadrs2 = r_rdadrs2;\r
- assign _u_FIFO_i_clock = i_clk50M;\r
- assign _u_FIFO_i_re1 = fs_fifo1_read;\r
- assign _u_FIFO_i_re2 = fs_fifo2_read;\r
- assign _net_0 = r_vcnt_hld&(~(r_vcnt[0]));\r
- assign _net_1 = (~r_vcnt_hld)&(r_vcnt[0]);\r
- assign _net_2 = (cnt)==(26'b01011111010111100001000000);\r
- assign _net_3 = ~_net_2;\r
- assign _net_4 = (r_hcnt) < (10'b1100100000);\r
- assign _net_5 = ~_net_4;\r
+ assign fs_fifo_read = _net_59|_reg_56|_net_15;\r
+ assign w_rddata = _u_FIFO_o_rddata;\r
+ assign fs_fifo_ack = _reg_64;\r
+ assign fs_initialize = _net_0;\r
+ assign _u_FIFO_i_rst = i_fifo_rst;\r
+ assign _u_FIFO_i_clk50 = i_clk50;\r
+ assign _u_FIFO_i_clk25 = m_clock;\r
+ assign _u_FIFO_i_we = fi_fifo_write;\r
+ assign _u_FIFO_i_wrdata = i_wrdata;\r
+ assign _u_FIFO_i_re = fs_fifo_read;\r
+ assign _net_0 = (r_trg)==(3'b011);\r
+ assign _net_1 = (r_cnt)==(26'b01011111010111100001000000);\r
+ assign _net_2 = ~_net_1;\r
+ assign _net_3 = (r_hcnt) < (10'b1100100000);\r
+ assign _net_4 = r_init_flg&_net_3;\r
+ assign _net_5 = r_init_flg&(~_net_3);\r
assign _net_6 = (r_vcnt) < (10'b1000001001);\r
- assign _net_7 = ~_net_4;\r
- assign _net_8 = (~_net_4)&_net_6;\r
- assign _net_9 = (~_net_4)&(~_net_6);\r
+ assign _net_7 = r_init_flg&(~_net_3);\r
+ assign _net_8 = (r_init_flg&(~_net_3))&_net_6;\r
+ assign _net_9 = (r_init_flg&(~_net_3))&(~_net_6);\r
assign _net_10 = ((r_hcnt) < (10'b1010000000))&((r_vcnt) < (10'b0111100000));\r
- assign _net_11 = r_vcnt[0];\r
- assign _net_12 = _net_10&_net_11;\r
- assign _net_13 = ~(r_vcnt[0]);\r
- assign _net_14 = _net_10&_net_13;\r
- assign _net_15 = (r_bit_number)==(5'b10111);\r
- assign _net_16 = _net_10&_net_15;\r
- assign _net_17 = r_vcnt[0];\r
- assign _net_18 = _net_10&_net_15;\r
- assign _net_19 = (_net_10&_net_15)&_net_17;\r
- assign _net_20 = ~(r_vcnt[0]);\r
- assign _net_21 = _net_10&_net_15;\r
- assign _net_22 = (_net_10&_net_15)&_net_20;\r
- assign _net_23 = _net_10&(~_net_15);\r
- assign _net_24 = (r_hcnt)==(10'b1011110000);\r
- assign _net_25 = ~_net_10;\r
- assign _net_26 = (~_net_10)&_net_24;\r
- assign _net_27 = (r_hcnt)==(10'b1010010000);\r
- assign _net_28 = ~_net_10;\r
- assign _net_29 = (~_net_10)&_net_27;\r
- assign _net_30 = (r_hcnt)==(10'b1010000000);\r
- assign _net_31 = ~_net_10;\r
- assign _net_32 = (~_net_10)&_net_30;\r
- assign _net_33 = (~_net_10)&_net_30;\r
- assign _net_34 = (~_net_10)&_net_30;\r
- assign _net_35 = (~_net_10)&_net_30;\r
- assign _net_36 = (~_net_10)&_net_30;\r
- assign _net_37 = (~_net_10)&_net_30;\r
- assign _net_38 = (r_vcnt)==(10'b0111101100);\r
- assign _net_39 = (r_vcnt)==(10'b0111101010);\r
- assign _net_40 = (r_vcnt)==(10'b0111100000);\r
- assign _net_41 = w_rddata1[r_bit_number];\r
- assign _net_42 = fs_fifo1_exec&_net_41;\r
- assign _net_43 = fs_fifo1_exec&_net_41;\r
- assign _net_44 = fs_fifo1_exec&_net_41;\r
- assign _net_45 = fs_fifo1_exec&(~_net_41);\r
- assign _net_46 = fs_fifo1_exec&(~_net_41);\r
- assign _net_47 = fs_fifo1_exec&(~_net_41);\r
- assign _net_48 = w_rddata2[r_bit_number];\r
- assign _net_49 = fs_fifo2_exec&_net_48;\r
- assign _net_50 = fs_fifo2_exec&_net_48;\r
- assign _net_51 = fs_fifo2_exec&_net_48;\r
- assign _net_52 = fs_fifo2_exec&(~_net_48);\r
- assign _net_53 = fs_fifo2_exec&(~_net_48);\r
- assign _net_54 = fs_fifo2_exec&(~_net_48);\r
+ assign _net_11 = _net_10&r_init_flg;\r
+ assign _net_12 = (r_bit_cnt)==(3'b111);\r
+ assign _net_13 = _net_10&r_init_flg;\r
+ assign _net_14 = (_net_10&r_init_flg)&_net_12;\r
+ assign _net_15 = (_net_10&r_init_flg)&_net_12;\r
+ assign _net_16 = ((_net_10&r_init_flg)&fs_fifo_ack)&r_reg_cnt;\r
+ assign _net_17 = ~r_reg_cnt;\r
+ assign _net_18 = (_net_10&r_init_flg)&fs_fifo_ack;\r
+ assign _net_19 = ((_net_10&r_init_flg)&fs_fifo_ack)&_net_17;\r
+ assign _net_20 = (r_reg_cnt)==(1'b0);\r
+ assign _net_21 = _net_10&r_init_flg;\r
+ assign _net_22 = (_net_10&r_init_flg)&_net_20;\r
+ assign _net_23 = (_net_10&r_init_flg)&(~_net_20);\r
+ assign _net_24 = (r_outcnt) < (3'b100);\r
+ assign _net_25 = _net_10&_net_24;\r
+ assign _net_26 = _net_10&(~_net_24);\r
+ assign _net_27 = _net_10&(~_net_24);\r
+ assign _net_28 = ~(r_outclr[4]);\r
+ assign _net_29 = _net_10&_net_28;\r
+ assign _net_30 = _net_10&(~_net_28);\r
+ assign _net_31 = ~(r_outclr[5]);\r
+ assign _net_32 = _net_10&_net_31;\r
+ assign _net_33 = _net_10&(~_net_31);\r
+ assign _net_34 = ~(r_outclr[6]);\r
+ assign _net_35 = _net_10&_net_34;\r
+ assign _net_36 = _net_10&(~_net_34);\r
+ assign _net_37 = (r_hcnt)==(10'b1011110000);\r
+ assign _net_38 = ~_net_10;\r
+ assign _net_39 = (~_net_10)&_net_37;\r
+ assign _net_40 = (r_hcnt)==(10'b1010010000);\r
+ assign _net_41 = ~_net_10;\r
+ assign _net_42 = (~_net_10)&_net_40;\r
+ assign _net_43 = (r_hcnt)==(10'b1010000000);\r
+ assign _net_44 = ~_net_10;\r
+ assign _net_45 = (~_net_10)&_net_43;\r
+ assign _net_46 = (~_net_10)&_net_43;\r
+ assign _net_47 = (~_net_10)&_net_43;\r
+ assign _net_48 = (~_net_10)&_net_43;\r
+ assign _net_49 = (~_net_10)&_net_43;\r
+ assign _net_50 = (~_net_10)&_net_43;\r
+ assign _net_51 = (r_vcnt)==(10'b0111101100);\r
+ assign _net_52 = (r_vcnt)==(10'b0111101010);\r
+ assign _net_53 = (r_vcnt)==(10'b0111100000);\r
+ assign _net_59 = fs_initialize|_reg_58;\r
+ assign _net_60 = fs_initialize|_reg_57|_reg_58;\r
+ assign _net_61 = fs_initialize|_reg_56|_reg_57;\r
+ assign _net_62 = fs_initialize|_reg_55|_reg_56;\r
+ assign _net_63 = fs_initialize|_reg_54|_reg_55;\r
+ assign _net_66 = fs_fifo_read|_reg_64|_reg_65;\r
assign o_vsync = r_vsync;\r
assign o_hsync = r_hsync;\r
- assign o_vga_r = ((_net_49|_net_42)?4'b1111:4'b0)|\r
- ((_net_52|_net_45|_net_32)?4'b0000:4'b0);\r
- assign o_vga_g = ((_net_50|_net_43)?4'b1111:4'b0)|\r
- ((_net_53|_net_46|_net_33)?4'b0000:4'b0);\r
- assign o_vga_b = ((_net_51|_net_44)?4'b1111:4'b0)|\r
- ((_net_54|_net_47|_net_34)?4'b0000:4'b0);\r
- assign outled = testled;\r
+ assign o_vga_r = ((_net_45|_net_33)?4'b0000:4'b0)|\r
+ ((_net_32)?~(r_outclr[3:0]):4'b0);\r
+ assign o_vga_g = ((_net_46|_net_36)?4'b0000:4'b0)|\r
+ ((_net_35)?~(r_outclr[3:0]):4'b0);\r
+ assign o_vga_b = ((_net_47|_net_30)?4'b0000:4'b0)|\r
+ ((_net_29)?~(r_outclr[3:0]):4'b0);\r
+ assign o_dummy_rgb = ((_net_50)?3'b000:3'b0)|\r
+ ((_net_23)?{{2{r_data2[r_bit_cnt]}},r_data2[r_bit_cnt]}:3'b0)|\r
+ ((_net_22)?{{2{r_data1[r_bit_cnt]}},r_data1[r_bit_cnt]}:3'b0);\r
assign o_vcnt = r_vcnt;\r
+ assign o_rdack = _u_FIFO_o_rdack;\r
+ assign o_led = r_led;\r
always @(posedge m_clock or posedge p_reset)\r
begin\r
if (p_reset)\r
- r_bit_number <= 5'b00000;\r
-else if ((_net_23)|(_net_37|_net_16)) \r
- r_bit_number <= ((_net_23) ?(r_bit_number)+(5'b00001):5'b0)|\r
- ((_net_37|_net_16) ?5'b00000:5'b0);\r
+ r_data1 <= 8'b00000000;\r
+else if ((_reg_57)|(_net_16)) \r
+ r_data1 <= ((_reg_57) ?_u_FIFO_o_rddata:8'b0)|\r
+ ((_net_16) ?w_rddata:8'b0);\r
\r
end\r
always @(posedge m_clock or posedge p_reset)\r
begin\r
if (p_reset)\r
+ r_data2 <= 8'b00000000;\r
+else if ((_reg_55)|(_net_19)) \r
+ r_data2 <= ((_reg_55) ?_u_FIFO_o_rddata:8'b0)|\r
+ ((_net_19) ?w_rddata:8'b0);\r
+\r
+end\r
+always @(posedge m_clock or posedge p_reset)\r
+ begin\r
+if (p_reset)\r
+ r_reg_cnt <= 1'b0;\r
+else if ((_net_14)) \r
+ r_reg_cnt <= ~r_reg_cnt;\r
+end\r
+always @(posedge m_clock or posedge p_reset)\r
+ begin\r
+if (p_reset)\r
+ r_bit_cnt <= 3'b000;\r
+else if ((_net_11)) \r
+ r_bit_cnt <= (r_bit_cnt)+(3'b001);\r
+end\r
+always @(posedge m_clock or posedge p_reset)\r
+ begin\r
+if (p_reset)\r
r_vsync <= 1'b0;\r
-else if ((_net_39)|(_net_38)) \r
- r_vsync <= ((_net_39) ?1'b0:1'b0)|\r
- ((_net_38) ?1'b1:1'b0);\r
+else if ((_net_52)|(_net_51)) \r
+ r_vsync <= ((_net_52) ?1'b0:1'b0)|\r
+ ((_net_51) ?1'b1:1'b0);\r
\r
end\r
always @(posedge m_clock or posedge p_reset)\r
begin\r
if (p_reset)\r
r_hsync <= 1'b0;\r
-else if ((_net_29)|(_net_26)) \r
- r_hsync <= ((_net_29) ?1'b0:1'b0)|\r
- ((_net_26) ?1'b1:1'b0);\r
+else if ((_net_42)|(_net_39)) \r
+ r_hsync <= ((_net_42) ?1'b0:1'b0)|\r
+ ((_net_39) ?1'b1:1'b0);\r
\r
end\r
always @(posedge m_clock or posedge p_reset)\r
always @(posedge m_clock or posedge p_reset)\r
begin\r
if (p_reset)\r
- cnt <= 26'b00000000000000000000000000;\r
-else if ((_net_3)|(_net_2)) \r
- cnt <= ((_net_3) ?(cnt)+(26'b00000000000000000000000001):26'b0)|\r
- ((_net_2) ?26'b00000000000000000000000000:26'b0);\r
+ r_cnt <= 26'b00000000000000000000000000;\r
+else if ((_net_2)|(_net_1)) \r
+ r_cnt <= ((_net_2) ?(r_cnt)+(26'b00000000000000000000000001):26'b0)|\r
+ ((_net_1) ?26'b00000000000000000000000000:26'b0);\r
\r
end\r
always @(posedge m_clock or posedge p_reset)\r
begin\r
if (p_reset)\r
- testled <= 1'b0;\r
-else if ((_net_2)) \r
- testled <= ~testled;\r
+ r_outcnt <= 3'b000;\r
+else if ((_net_48|_net_26)|(_net_25)) \r
+ r_outcnt <= ((_net_48|_net_26) ?3'b000:3'b0)|\r
+ ((_net_25) ?(r_outcnt)+(3'b001):3'b0);\r
+\r
end\r
always @(posedge m_clock or posedge p_reset)\r
begin\r
if (p_reset)\r
- r_outcnt <= 3'b000;\r
-else if ((_net_35)) \r
- r_outcnt <= 3'b000;\r
+ r_outclr <= 7'b0000000;\r
+else if ((_net_49)|(_net_27)) \r
+ r_outclr <= ((_net_49) ?7'b0000000:7'b0)|\r
+ ((_net_27) ?(r_outclr)+(7'b0000001):7'b0);\r
+\r
+end\r
+always @(posedge p_reset)\r
+ begin\r
+if (p_reset)\r
+ r_vcnt_hld <= 1'b0;\r
end\r
always @(posedge m_clock or posedge p_reset)\r
begin\r
if (p_reset)\r
- r_outclr <= 7'b0000000;\r
-else if ((_net_36)) \r
- r_outclr <= 7'b0000000;\r
+ r_led <= 1'b0;\r
+else if ((_net_1)) \r
+ r_led <= ~r_led;\r
end\r
always @(posedge m_clock or posedge p_reset)\r
begin\r
if (p_reset)\r
- r_vcnt_hld <= 1'b0;\r
-else r_vcnt_hld <= r_vcnt[0];\r
+ r_init_flg <= 1'b0;\r
+else if ((_reg_54)) \r
+ r_init_flg <= 1'b1;\r
+end\r
+always @(posedge m_clock or posedge p_reset)\r
+ begin\r
+if (p_reset)\r
+ r_trg <= 3'b000;\r
+else r_trg <= {r_trg[1:0],1'b1};\r
+end\r
+always @(posedge m_clock or posedge p_reset)\r
+ begin\r
+if (p_reset)\r
+ _reg_54 <= 1'b0;\r
+else if ((_net_63)) \r
+ _reg_54 <= _reg_55;\r
+end\r
+always @(posedge m_clock or posedge p_reset)\r
+ begin\r
+if (p_reset)\r
+ _reg_55 <= 1'b0;\r
+else if ((_net_62)) \r
+ _reg_55 <= _reg_56;\r
+end\r
+always @(posedge m_clock or posedge p_reset)\r
+ begin\r
+if (p_reset)\r
+ _reg_56 <= 1'b0;\r
+else if ((_net_61)) \r
+ _reg_56 <= _reg_57;\r
+end\r
+always @(posedge m_clock or posedge p_reset)\r
+ begin\r
+if (p_reset)\r
+ _reg_57 <= 1'b0;\r
+else if ((_net_60)) \r
+ _reg_57 <= _reg_58|fs_initialize;\r
+end\r
+always @(posedge m_clock or posedge p_reset)\r
+ begin\r
+if (p_reset)\r
+ _reg_58 <= 1'b0;\r
+else if ((_reg_58)) \r
+ _reg_58 <= 1'b0;\r
end\r
always @(posedge m_clock or posedge p_reset)\r
begin\r
if (p_reset)\r
- r_rdadrs1 <= 8'b00000000;\r
-else if ((fs_fifo1_reset)|(fs_fifo1_read)) \r
- r_rdadrs1 <= ((fs_fifo1_reset) ?8'b00000000:8'b0)|\r
- ((fs_fifo1_read) ?(r_rdadrs1)+(8'b00000011):8'b0);\r
+ _reg_64 <= 1'b0;\r
+else if ((_net_66)) \r
+ _reg_64 <= _reg_65|fs_fifo_read;\r
+end\r
+always @(posedge m_clock or posedge p_reset)\r
+ begin\r
+if (p_reset)\r
+ _reg_65 <= 1'b0;\r
+else if ((_reg_65)) \r
+ _reg_65 <= 1'b0;\r
+end\r
+endmodule\r
+/*\r
+ Produced by NSL Core(version=20110302), IP ARCH, Inc. Sun Nov 06 16:37:30 2011\r
+ Licensed to Yujiro_Kaneko::yujiro.kaneko@overtone.co.jp \r
+*/\r
+\r
+module push_sw ( p_reset , m_clock , i_sw , fo_sw_enb );\r
+ input p_reset, m_clock;\r
+ input i_sw;\r
+ output fo_sw_enb;\r
+ reg [18:0] r_cnt;\r
+ reg r_rise_flag;\r
+ reg r_sw_hld;\r
+ reg r_finish_flag;\r
+ wire _net_67;\r
+ wire _net_68;\r
+ wire _net_69;\r
+ wire _net_70;\r
+ wire _net_71;\r
+ wire _net_72;\r
+ wire _net_73;\r
+ wire _net_74;\r
+ wire _net_75;\r
+ wire _net_76;\r
+ wire _net_77;\r
+\r
+ assign _net_67 = i_sw&(~r_sw_hld);\r
+ assign _net_68 = ~i_sw;\r
+ assign _net_69 = ~_net_67;\r
+ assign _net_70 = (~_net_67)&_net_68;\r
+ assign _net_71 = (~_net_67)&_net_68;\r
+ assign _net_72 = (r_rise_flag)==(1'b1);\r
+ assign _net_73 = ((r_cnt)==(19'b1111010000100100000))&((r_finish_flag)==(1'b0));\r
+ assign _net_74 = _net_72&_net_73;\r
+ assign _net_75 = _net_72&_net_73;\r
+ assign _net_76 = _net_72&(~_net_73);\r
+ assign _net_77 = ~_net_72;\r
+ assign fo_sw_enb = _net_75;\r
+always @(posedge m_clock or posedge p_reset)\r
+ begin\r
+if (p_reset)\r
+ r_cnt <= 19'b0000000000000000000;\r
+else if ((_net_77)|(_net_76)) \r
+ r_cnt <= ((_net_77) ?26'b00000000000000000000000000:19'b0)|\r
+ ((_net_76) ?(r_cnt)+(19'b0000000000000000001):19'b0);\r
+\r
+end\r
+always @(posedge m_clock or posedge p_reset)\r
+ begin\r
+if (p_reset)\r
+ r_rise_flag <= 1'b0;\r
+else if ((_net_70)|(_net_67)) \r
+ r_rise_flag <= ((_net_70) ?1'b0:1'b0)|\r
+ ((_net_67) ?1'b1:1'b0);\r
\r
end\r
always @(posedge m_clock or posedge p_reset)\r
begin\r
if (p_reset)\r
- r_rdadrs2 <= 8'b00000000;\r
-else if ((fs_fifo2_reset)|(fs_fifo2_read)) \r
- r_rdadrs2 <= ((fs_fifo2_reset) ?8'b00000000:8'b0)|\r
- ((fs_fifo2_read) ?(r_rdadrs2)+(8'b00000011):8'b0);\r
+ r_sw_hld <= 1'b0;\r
+else r_sw_hld <= i_sw;\r
+end\r
+always @(posedge m_clock or posedge p_reset)\r
+ begin\r
+if (p_reset)\r
+ r_finish_flag <= 1'b0;\r
+else if ((_net_74)|(_net_71)) \r
+ r_finish_flag <= ((_net_74) ?1'b1:1'b0)|\r
+ ((_net_71) ?1'b0:1'b0);\r
\r
end\r
endmodule\r
/*\r
- Produced by NSL Core(version=20110302), IP ARCH, Inc. Wed Sep 21 22:08:00 2011\r
- Licensed to Yujiro_Kaneko::zyangalianhamster01@gmail.com \r
+ Produced by NSL Core(version=20110302), IP ARCH, Inc. Sun Nov 06 16:37:31 2011\r
+ Licensed to Yujiro_Kaneko::yujiro.kaneko@overtone.co.jp \r
*/\r
\r
module vga_top ( p_reset , m_clock , i_sw , o_vsync , o_hsync , o_vga_r , o_vga_g , o_vga_b , o_LED );\r
input p_reset, m_clock;\r
- input i_sw;\r
+ input [3:0] i_sw;\r
output o_vsync;\r
output o_hsync;\r
output [3:0] o_vga_r;\r
reg [15:0] r_vram_rddata;\r
reg [13:0] r_vram_start_adrs;\r
reg r_hld_vram_start;\r
+ reg r_fifo_rst;\r
wire [7:0] w_wrdata1;\r
wire [7:0] w_wrdata2;\r
wire [7:0] w_wradrs1;\r
wire fs_vram_cnt_inc;\r
reg [7:0] r_wradrs1;\r
reg [7:0] r_wradrs2;\r
+ reg r_out_sel;\r
wire test_write;\r
reg [25:0] r_wait_cnt;\r
reg [25:0] r_wait_val;\r
reg p_wait;\r
- wire [13:0] _net_57;\r
- wire [13:0] _net_60;\r
- wire [13:0] _net_63;\r
- wire [13:0] _net_66;\r
- wire [13:0] _net_69;\r
+ wire [13:0] _net_80;\r
wire _proc_p_wait_set;\r
wire _proc_p_wait_reset;\r
- wire _net_70;\r
- wire _u_VGA_i_clk50M;\r
+ wire _net_81;\r
+ wire _u_VGA_i_clk50;\r
+ wire _u_VGA_i_fifo_rst;\r
wire _u_VGA_m_clock;\r
wire _u_VGA_p_reset;\r
wire _u_VGA_o_vsync;\r
wire [3:0] _u_VGA_o_vga_r;\r
wire [3:0] _u_VGA_o_vga_g;\r
wire [3:0] _u_VGA_o_vga_b;\r
- wire [7:0] _u_VGA_i_wrdata1;\r
- wire [7:0] _u_VGA_i_wrdata2;\r
- wire [7:0] _u_VGA_i_wradrs1;\r
- wire [7:0] _u_VGA_i_wradrs2;\r
- wire _u_VGA_fi_fifo1_write;\r
- wire _u_VGA_fi_fifo2_write;\r
- wire _u_VGA_outled;\r
+ wire [2:0] _u_VGA_o_dummy_rgb;\r
wire [9:0] _u_VGA_o_vcnt;\r
- wire [13:0] _u_EXP_i_Radrs;\r
- wire [15:0] _u_EXP_o_Rdata;\r
- wire _u_EXP_fi_Rd_req;\r
- wire _u_EXP_fo_Rd_ack;\r
- wire [7:0] _u_EXP_i_Wdata;\r
- wire [13:0] _u_EXP_i_Wadrs;\r
- wire _u_EXP_fi_Wr_req;\r
- wire _u_EXP_p_reset;\r
- wire _u_EXP_m_clock;\r
- wire _net_71;\r
- wire _net_72;\r
- wire _net_73;\r
- wire _net_74;\r
- wire _net_75;\r
- wire _net_76;\r
- wire _net_77;\r
- wire _net_78;\r
- wire _net_79;\r
- wire _net_80;\r
- wire _net_81;\r
+ wire [7:0] _u_VGA_i_wrdata;\r
+ wire _u_VGA_fi_fifo_write;\r
+ wire _u_VGA_o_rdack;\r
+ wire _u_VGA_o_led;\r
+ wire _u_BTN_i_sw;\r
+ wire _u_BTN_fo_sw_enb;\r
+ wire _u_BTN_p_reset;\r
+ wire _u_BTN_m_clock;\r
+ wire _u_BTN_3_i_sw;\r
+ wire _u_BTN_3_fo_sw_enb;\r
+ wire _u_BTN_3_p_reset;\r
+ wire _u_BTN_3_m_clock;\r
+ wire _u_BTN_2_i_sw;\r
+ wire _u_BTN_2_fo_sw_enb;\r
+ wire _u_BTN_2_p_reset;\r
+ wire _u_BTN_2_m_clock;\r
+ wire _u_BTN_1_i_sw;\r
+ wire _u_BTN_1_fo_sw_enb;\r
+ wire _u_BTN_1_p_reset;\r
+ wire _u_BTN_1_m_clock;\r
wire _net_82;\r
- reg _reg_83;\r
- reg _reg_84;\r
- reg _reg_85;\r
- reg _reg_86;\r
- reg _reg_87;\r
- reg _reg_88;\r
+ wire _net_83;\r
+ wire _net_84;\r
+ wire _net_85;\r
+ wire _net_86;\r
+ wire _net_87;\r
+ wire _net_88;\r
reg _reg_89;\r
reg _reg_90;\r
reg _reg_91;\r
reg _reg_99;\r
reg _reg_100;\r
wire _net_101;\r
- wire _reg_86_goto;\r
+ wire _reg_90_goto;\r
wire _net_102;\r
- wire _reg_90_goin;\r
+ wire _reg_91_goin;\r
wire _net_103;\r
wire _net_104;\r
- wire _reg_90_goto;\r
+ wire _reg_91_goto;\r
wire _net_105;\r
- wire _reg_85_goin;\r
+ wire _reg_89_goin;\r
wire _net_106;\r
wire _net_107;\r
wire _net_108;\r
wire _net_109;\r
- wire _reg_93_goto;\r
wire _net_110;\r
- wire _reg_97_goin;\r
wire _net_111;\r
wire _net_112;\r
- wire _reg_97_goto;\r
wire _net_113;\r
- wire _reg_92_goin;\r
wire _net_114;\r
wire _net_115;\r
wire _net_116;\r
wire _net_117;\r
- wire _reg_99_goto;\r
wire _net_118;\r
- wire _reg_98_goin;\r
wire _net_119;\r
wire _net_120;\r
wire _net_121;\r
wire _net_122;\r
wire _net_123;\r
wire _net_124;\r
- wire _reg_99_goin;\r
- wire _net_125;\r
- wire _net_126;\r
- wire _net_127;\r
- wire _net_128;\r
- wire _net_129;\r
- wire _net_130;\r
- wire _net_131;\r
- wire _net_132;\r
- wire _net_133;\r
- wire _net_134;\r
- wire _net_135;\r
- wire _net_136;\r
- wire _net_137;\r
- wire _net_138;\r
- wire _net_139;\r
- wire _net_140;\r
- wire _net_141;\r
- wire _net_142;\r
- wire _net_143;\r
- wire _net_144;\r
- wire _net_145;\r
- wire _net_146;\r
- reg _reg_147;\r
- reg _reg_148;\r
- reg _reg_149;\r
- reg _reg_150;\r
- reg _reg_151;\r
- reg _reg_152;\r
- reg _reg_153;\r
- reg _reg_154;\r
- wire _net_155;\r
- wire _net_156;\r
- wire _net_157;\r
- wire _reg_149_goto;\r
- wire _net_158;\r
- wire _reg_153_goin;\r
- wire _net_159;\r
- wire _net_160;\r
- wire _reg_153_goto;\r
- wire _net_161;\r
- wire _reg_148_goin;\r
- wire _net_162;\r
- wire _net_163;\r
- wire _net_164;\r
- wire _net_165;\r
- wire _net_166;\r
- wire _net_167;\r
- wire _net_168;\r
- wire _net_169;\r
- wire _net_170;\r
- wire _net_171;\r
- wire _net_172;\r
- reg _reg_173;\r
- reg _reg_174;\r
- reg _reg_175;\r
- reg _reg_176;\r
- reg _reg_177;\r
- reg _reg_178;\r
- reg _reg_179;\r
- reg _reg_180;\r
- reg _reg_181;\r
- wire _net_182;\r
- wire _net_183;\r
- wire _net_184;\r
- wire _reg_176_goto;\r
- wire _net_185;\r
- wire _reg_180_goin;\r
- wire _net_186;\r
- wire _net_187;\r
- wire _reg_180_goto;\r
- wire _net_188;\r
- wire _reg_175_goin;\r
- wire _net_189;\r
- wire _net_190;\r
- wire _net_191;\r
- wire _net_192;\r
- wire _net_193;\r
- wire _net_194;\r
- wire _net_195;\r
- wire _net_196;\r
- wire _net_197;\r
- wire _net_198;\r
- wire _net_199;\r
- wire _net_200;\r
- wire _net_201;\r
- wire _net_202;\r
- wire _net_203;\r
- wire _net_204;\r
- wire _net_205;\r
- wire _net_206;\r
- wire _net_207;\r
-exp_ctrl u_EXP (.p_reset(p_reset), .m_clock(m_clock), .fi_Wr_req(_u_EXP_fi_Wr_req), .i_Wadrs(_u_EXP_i_Wadrs), .i_Wdata(_u_EXP_i_Wdata), .fo_Rd_ack(_u_EXP_fo_Rd_ack), .fi_Rd_req(_u_EXP_fi_Rd_req), .o_Rdata(_u_EXP_o_Rdata), .i_Radrs(_u_EXP_i_Radrs));\r
-vga_gen u_VGA (.o_vcnt(_u_VGA_o_vcnt), .outled(_u_VGA_outled), .fi_fifo2_write(_u_VGA_fi_fifo2_write), .fi_fifo1_write(_u_VGA_fi_fifo1_write), .i_wradrs2(_u_VGA_i_wradrs2), .i_wradrs1(_u_VGA_i_wradrs1), .i_wrdata2(_u_VGA_i_wrdata2), .i_wrdata1(_u_VGA_i_wrdata1), .o_vga_b(_u_VGA_o_vga_b), .o_vga_g(_u_VGA_o_vga_g), .o_vga_r(_u_VGA_o_vga_r), .o_hsync(_u_VGA_o_hsync), .o_vsync(_u_VGA_o_vsync), .p_reset(_u_VGA_p_reset), .m_clock(_u_VGA_m_clock), .i_clk50M(_u_VGA_i_clk50M));\r
+push_sw u_BTN (.p_reset(p_reset), .m_clock(m_clock), .fo_sw_enb(_u_BTN_fo_sw_enb), .i_sw(_u_BTN_i_sw));\r
+push_sw u_BTN_3 (.p_reset(p_reset), .m_clock(m_clock), .fo_sw_enb(_u_BTN_3_fo_sw_enb), .i_sw(_u_BTN_3_i_sw));\r
+push_sw u_BTN_2 (.p_reset(p_reset), .m_clock(m_clock), .fo_sw_enb(_u_BTN_2_fo_sw_enb), .i_sw(_u_BTN_2_i_sw));\r
+push_sw u_BTN_1 (.p_reset(p_reset), .m_clock(m_clock), .fo_sw_enb(_u_BTN_1_fo_sw_enb), .i_sw(_u_BTN_1_i_sw));\r
+vga_gen u_VGA (.o_led(_u_VGA_o_led), .o_rdack(_u_VGA_o_rdack), .fi_fifo_write(_u_VGA_fi_fifo_write), .i_wrdata(_u_VGA_i_wrdata), .o_vcnt(_u_VGA_o_vcnt), .o_dummy_rgb(_u_VGA_o_dummy_rgb), .o_vga_b(_u_VGA_o_vga_b), .o_vga_g(_u_VGA_o_vga_g), .o_vga_r(_u_VGA_o_vga_r), .o_hsync(_u_VGA_o_hsync), .o_vsync(_u_VGA_o_vsync), .p_reset(_u_VGA_p_reset), .m_clock(_u_VGA_m_clock), .i_fifo_rst(_u_VGA_i_fifo_rst), .i_clk50(_u_VGA_i_clk50));\r
\r
- assign w_wrdata1 = ((_reg_150|_reg_95)?r_vram_rddata[15:8]:8'b0)|\r
- ((_reg_151|_reg_94)?r_vram_rddata[7:0]:8'b0);\r
- assign w_wrdata2 = ((_reg_177|_reg_88)?r_vram_rddata[15:8]:8'b0)|\r
- ((_reg_178|_reg_87)?r_vram_rddata[7:0]:8'b0);\r
- assign w_wradrs1 = r_wradrs1;\r
- assign w_wradrs2 = r_wradrs2;\r
- assign fs_fifo1_write = _reg_151|_reg_150|_reg_95|_reg_94;\r
- assign fs_fifo2_write = _reg_178|_reg_177|_reg_88|_reg_87;\r
- assign fs_init = _net_71;\r
- assign fs_fifo1_charge = _net_76;\r
- assign fs_fifo2_charge = _net_80;\r
- assign fs_vram_cnt_inc = _reg_173;\r
+ assign fs_fifo1_write = 1'b0;\r
+ assign fs_fifo2_write = 1'b0;\r
+ assign fs_init = _net_86;\r
+ assign fs_fifo1_charge = 1'b0;\r
+ assign fs_fifo2_charge = 1'b0;\r
+ assign fs_vram_cnt_inc = 1'b0;\r
assign test_write = 1'b0;\r
- assign _net_57 = (r_init_cnt)+(14'b00000000000001);\r
- assign _net_60 = (r_init_cnt)+(14'b00000000000001);\r
- assign _net_63 = (r_init_cnt)+(14'b00000000000001);\r
- assign _net_66 = (r_init_cnt)+(14'b00000000000001);\r
- assign _net_69 = (r_init_cnt)+(14'b00000000000001);\r
+ assign _net_80 = (r_init_cnt)+(14'b00000000000001);\r
assign _proc_p_wait_set = 1'b0;\r
- assign _proc_p_wait_reset = _net_206;\r
- assign _net_70 = _proc_p_wait_set|_proc_p_wait_reset;\r
- assign _u_VGA_i_clk50M = m_clock;\r
+ assign _proc_p_wait_reset = _net_123;\r
+ assign _net_81 = _proc_p_wait_set|_proc_p_wait_reset;\r
+ assign _u_VGA_i_clk50 = m_clock;\r
+ assign _u_VGA_i_fifo_rst = r_fifo_rst;\r
assign _u_VGA_m_clock = r_cnt;\r
assign _u_VGA_p_reset = r_reset;\r
- assign _u_VGA_i_wrdata1 = w_wrdata1;\r
- assign _u_VGA_i_wrdata2 = w_wrdata2;\r
- assign _u_VGA_i_wradrs1 = w_wradrs1;\r
- assign _u_VGA_i_wradrs2 = w_wradrs2;\r
- assign _u_VGA_fi_fifo1_write = fs_fifo1_write;\r
- assign _u_VGA_fi_fifo2_write = fs_fifo2_write;\r
- assign _u_EXP_i_Radrs = ((_net_164|_net_116)?r_vram_adrs1:14'b0)|\r
- ((_net_191|_net_108)?r_vram_adrs2:14'b0);\r
- assign _u_EXP_fi_Rd_req = _net_190|_net_163|_net_115|_net_107;\r
- assign _u_EXP_i_Wdata = r_init_cnt[7:0];\r
- assign _u_EXP_i_Wadrs = r_init_cnt;\r
- assign _u_EXP_fi_Wr_req = _net_126;\r
- assign _net_71 = (trigger)==(3'b011);\r
- assign _net_72 = ~r_reset;\r
- assign _net_73 = (~r_hld_vram_start)&(_u_VGA_o_vcnt[0]);\r
- assign _net_74 = (_u_VGA_o_vcnt) < (10'b0111100000);\r
- assign _net_75 = _net_72&_net_73;\r
- assign _net_76 = (_net_72&_net_73)&_net_74;\r
- assign _net_77 = r_hld_vram_start&(~(_u_VGA_o_vcnt[0]));\r
- assign _net_78 = (_u_VGA_o_vcnt) < (10'b0111100000);\r
- assign _net_79 = _net_72&_net_77;\r
- assign _net_80 = (_net_72&_net_77)&_net_78;\r
- assign _net_81 = (r_sec_cnt)==(26'b10111110101111000010000000);\r
- assign _net_82 = ~_net_81;\r
- assign _net_101 = (_net_63) < (14'b00000000101000);\r
- assign _reg_86_goto = _net_102;\r
- assign _net_102 = _reg_86&_net_101;\r
- assign _reg_90_goin = _net_103;\r
- assign _net_103 = _reg_86&_net_101;\r
- assign _net_104 = ~((r_init_cnt) < (14'b00000000101000));\r
- assign _reg_90_goto = _net_105;\r
- assign _net_105 = _reg_90&_net_104;\r
- assign _reg_85_goin = _net_106;\r
- assign _net_106 = _reg_90&_net_104;\r
- assign _net_107 = _reg_90&(~_net_104);\r
- assign _net_108 = _reg_90&(~_net_104);\r
- assign _net_109 = (_net_60) < (14'b00000000101000);\r
- assign _reg_93_goto = _net_110;\r
- assign _net_110 = _reg_93&_net_109;\r
- assign _reg_97_goin = _net_111;\r
- assign _net_111 = _reg_93&_net_109;\r
- assign _net_112 = ~((r_init_cnt) < (14'b00000000101000));\r
- assign _reg_97_goto = _net_113;\r
- assign _net_113 = _reg_97&_net_112;\r
- assign _reg_92_goin = _net_114;\r
- assign _net_114 = _reg_97&_net_112;\r
- assign _net_115 = _reg_97&(~_net_112);\r
- assign _net_116 = _reg_97&(~_net_112);\r
- assign _net_117 = ~((r_init_cnt) < (14'b10010110000000));\r
- assign _reg_99_goto = _net_124|_net_118;\r
- assign _net_118 = _reg_99&_net_117;\r
- assign _reg_98_goin = _net_119;\r
- assign _net_119 = _reg_99&_net_117;\r
- assign _net_120 = _reg_99&(~_net_117);\r
- assign _net_121 = _reg_99&(~_net_117);\r
- assign _net_122 = (_net_57) < (14'b10010110000000);\r
- assign _net_123 = _reg_99&(~_net_117);\r
- assign _net_124 = (_reg_99&(~_net_117))&_net_122;\r
- assign _reg_99_goin = _net_125;\r
- assign _net_125 = (_reg_99&(~_net_117))&_net_122;\r
- assign _net_126 = _reg_99&(~_net_117);\r
- assign _net_127 = _reg_99&(~_net_117);\r
- assign _net_128 = _reg_99&(~_net_117);\r
- assign _net_129 = fs_init|_reg_100;\r
- assign _net_130 = (_reg_99_goin|fs_init)|_reg_99|_reg_100;\r
- assign _net_131 = _reg_98_goin|_reg_98|_reg_99;\r
- assign _net_132 = _reg_97_goin|_reg_97|_reg_98;\r
- assign _net_133 = _reg_97_goin|_reg_96|_reg_97;\r
- assign _net_134 = _reg_97_goin|_reg_95|_reg_96;\r
- assign _net_135 = _reg_97_goin|_reg_94|_reg_95;\r
- assign _net_136 = _reg_97_goin|_reg_93|_reg_94;\r
- assign _net_137 = _reg_92_goin|_reg_92|_reg_93;\r
- assign _net_138 = _reg_92_goin|_reg_91|_reg_92;\r
- assign _net_139 = _reg_90_goin|_reg_90|_reg_91;\r
- assign _net_140 = _reg_90_goin|_reg_89|_reg_90;\r
- assign _net_141 = _reg_90_goin|_reg_88|_reg_89;\r
- assign _net_142 = _reg_90_goin|_reg_87|_reg_88;\r
- assign _net_143 = _reg_90_goin|_reg_86|_reg_87;\r
- assign _net_144 = _reg_85_goin|_reg_85|_reg_86;\r
- assign _net_145 = _reg_85_goin|_reg_84|_reg_85;\r
- assign _net_146 = _reg_85_goin|_reg_83|_reg_84;\r
- assign _net_155 = (r_vram_adrs1)==(14'b10010110000000);\r
- assign _net_156 = _reg_147&_net_155;\r
- assign _net_157 = (_net_66) < (14'b00000000101000);\r
- assign _reg_149_goto = _net_158;\r
- assign _net_158 = _reg_149&_net_157;\r
- assign _reg_153_goin = _net_159;\r
- assign _net_159 = _reg_149&_net_157;\r
- assign _net_160 = ~((r_init_cnt) < (14'b00000000101000));\r
- assign _reg_153_goto = _net_161;\r
- assign _net_161 = _reg_153&_net_160;\r
- assign _reg_148_goin = _net_162;\r
- assign _net_162 = _reg_153&_net_160;\r
- assign _net_163 = _reg_153&(~_net_160);\r
- assign _net_164 = _reg_153&(~_net_160);\r
- assign _net_165 = fs_fifo1_charge|_reg_154;\r
- assign _net_166 = (_reg_153_goin|fs_fifo1_charge)|_reg_153|_reg_154;\r
- assign _net_167 = (_reg_153_goin|fs_fifo1_charge)|_reg_152|_reg_153;\r
- assign _net_168 = (_reg_153_goin|fs_fifo1_charge)|_reg_151|_reg_152;\r
- assign _net_169 = (_reg_153_goin|fs_fifo1_charge)|_reg_150|_reg_151;\r
- assign _net_170 = (_reg_153_goin|fs_fifo1_charge)|_reg_149|_reg_150;\r
- assign _net_171 = _reg_148_goin|_reg_148|_reg_149;\r
- assign _net_172 = _reg_148_goin|_reg_147|_reg_148;\r
- assign _net_182 = (r_vram_adrs2)==(14'b10010110000000);\r
- assign _net_183 = _reg_174&_net_182;\r
- assign _net_184 = (_net_69) < (14'b00000000101000);\r
- assign _reg_176_goto = _net_185;\r
- assign _net_185 = _reg_176&_net_184;\r
- assign _reg_180_goin = _net_186;\r
- assign _net_186 = _reg_176&_net_184;\r
- assign _net_187 = ~((r_init_cnt) < (14'b00000000101000));\r
- assign _reg_180_goto = _net_188;\r
- assign _net_188 = _reg_180&_net_187;\r
- assign _reg_175_goin = _net_189;\r
- assign _net_189 = _reg_180&_net_187;\r
- assign _net_190 = _reg_180&(~_net_187);\r
- assign _net_191 = _reg_180&(~_net_187);\r
- assign _net_192 = fs_fifo2_charge|_reg_181;\r
- assign _net_193 = (_reg_180_goin|fs_fifo2_charge)|_reg_180|_reg_181;\r
- assign _net_194 = (_reg_180_goin|fs_fifo2_charge)|_reg_179|_reg_180;\r
- assign _net_195 = (_reg_180_goin|fs_fifo2_charge)|_reg_178|_reg_179;\r
- assign _net_196 = (_reg_180_goin|fs_fifo2_charge)|_reg_177|_reg_178;\r
- assign _net_197 = (_reg_180_goin|fs_fifo2_charge)|_reg_176|_reg_177;\r
- assign _net_198 = _reg_175_goin|_reg_175|_reg_176;\r
- assign _net_199 = _reg_175_goin|_reg_174|_reg_175;\r
- assign _net_200 = _reg_175_goin|_reg_173|_reg_174;\r
- assign _net_201 = (r_vram_start_adrs)==(14'b10010101011000);\r
- assign _net_202 = fs_vram_cnt_inc&_net_201;\r
- assign _net_203 = fs_vram_cnt_inc&(~_net_201);\r
- assign _net_204 = (r_wait_cnt)==(r_wait_val);\r
- assign _net_205 = p_wait&_net_204;\r
- assign _net_206 = p_wait&_net_204;\r
- assign _net_207 = p_wait&(~_net_204);\r
+ assign _u_VGA_i_wrdata = r_init_cnt[7:0];\r
+ assign _u_VGA_fi_fifo_write = _net_107|_reg_90;\r
+ assign _u_BTN_i_sw = i_sw[0];\r
+ assign _u_BTN_3_i_sw = i_sw[3];\r
+ assign _u_BTN_2_i_sw = i_sw[2];\r
+ assign _u_BTN_1_i_sw = i_sw[1];\r
+ assign _net_82 = (r_out_sel)==(1'b0);\r
+ assign _net_83 = ~_net_82;\r
+ assign _net_84 = ~_net_82;\r
+ assign _net_85 = ~_net_82;\r
+ assign _net_86 = (trigger)==(3'b011);\r
+ assign _net_87 = (r_sec_cnt)==(26'b10111110101111000010000000);\r
+ assign _net_88 = ~_net_87;\r
+ assign _net_101 = (_net_80) < (14'b00001000000000);\r
+ assign _reg_90_goto = _net_102;\r
+ assign _net_102 = _reg_90&_net_101;\r
+ assign _reg_91_goin = _net_103;\r
+ assign _net_103 = _reg_90&_net_101;\r
+ assign _net_104 = ~((r_init_cnt) < (14'b00001000000000));\r
+ assign _reg_91_goto = _net_105;\r
+ assign _net_105 = _reg_91&_net_104;\r
+ assign _reg_89_goin = _net_106;\r
+ assign _net_106 = _reg_91&_net_104;\r
+ assign _net_107 = _reg_91&(~_net_104);\r
+ assign _net_108 = _reg_91&(~_net_104);\r
+ assign _net_109 = fs_init|_reg_100;\r
+ assign _net_110 = fs_init|_reg_99|_reg_100;\r
+ assign _net_111 = fs_init|_reg_98|_reg_99;\r
+ assign _net_112 = fs_init|_reg_97|_reg_98;\r
+ assign _net_113 = fs_init|_reg_96|_reg_97;\r
+ assign _net_114 = fs_init|_reg_95|_reg_96;\r
+ assign _net_115 = fs_init|_reg_94|_reg_95;\r
+ assign _net_116 = fs_init|_reg_93|_reg_94;\r
+ assign _net_117 = fs_init|_reg_92|_reg_93;\r
+ assign _net_118 = _reg_91_goin|_reg_91|_reg_92;\r
+ assign _net_119 = _reg_91_goin|_reg_90|_reg_91;\r
+ assign _net_120 = _reg_89_goin|_reg_89|_reg_90;\r
+ assign _net_121 = (r_wait_cnt)==(r_wait_val);\r
+ assign _net_122 = p_wait&_net_121;\r
+ assign _net_123 = p_wait&_net_121;\r
+ assign _net_124 = p_wait&(~_net_121);\r
assign o_vsync = _u_VGA_o_vsync;\r
assign o_hsync = _u_VGA_o_hsync;\r
- assign o_vga_r = _u_VGA_o_vga_r;\r
- assign o_vga_g = _u_VGA_o_vga_g;\r
- assign o_vga_b = _u_VGA_o_vga_b;\r
- assign o_LED = {5'b00000,i_sw,r_LED,_u_VGA_outled};\r
+ assign o_vga_r = ((_net_83)?_u_VGA_o_vga_r:4'b0)|\r
+ ((_net_82)?{{3{_u_VGA_o_dummy_rgb[2]}},_u_VGA_o_dummy_rgb[2]}:4'b0);\r
+ assign o_vga_g = ((_net_84)?_u_VGA_o_vga_g:4'b0)|\r
+ ((_net_82)?{{3{_u_VGA_o_dummy_rgb[1]}},_u_VGA_o_dummy_rgb[1]}:4'b0);\r
+ assign o_vga_b = ((_net_85)?_u_VGA_o_vga_b:4'b0)|\r
+ ((_net_82)?{{3{_u_VGA_o_dummy_rgb[0]}},_u_VGA_o_dummy_rgb[0]}:4'b0);\r
+ assign o_LED = {2'b00,i_sw,r_LED,_u_VGA_o_led};\r
always @(posedge m_clock or posedge p_reset)\r
begin\r
if (p_reset)\r
begin\r
if (p_reset)\r
r_reset <= 1'b1;\r
-else if ((_reg_83)) \r
+else if ((_reg_89)) \r
r_reset <= 1'b0;\r
end\r
always @(posedge m_clock or posedge p_reset)\r
begin\r
if (p_reset)\r
r_sec_cnt <= 26'b00000000000000000000000000;\r
-else if ((_net_82)|(_net_81)) \r
- r_sec_cnt <= ((_net_82) ?(r_sec_cnt)+(26'b00000000000000000000000001):26'b0)|\r
- ((_net_81) ?26'b00000000000000000000000000:26'b0);\r
+else if ((_net_88)|(_net_87)) \r
+ r_sec_cnt <= ((_net_88) ?(r_sec_cnt)+(26'b00000000000000000000000001):26'b0)|\r
+ ((_net_87) ?26'b00000000000000000000000000:26'b0);\r
\r
end\r
always @(posedge m_clock or posedge p_reset)\r
begin\r
if (p_reset)\r
r_LED <= 1'b0;\r
-else if ((_net_81)) \r
+else if ((_net_87)) \r
r_LED <= ~r_LED;\r
end\r
always @(posedge m_clock or posedge p_reset)\r
begin\r
if (p_reset)\r
r_init_cnt <= 14'b00000000000000;\r
-else if ((_reg_176)|(_reg_149)|(_net_120)|(_reg_93)|(_net_192|_net_165|_net_129|_reg_98|_reg_91)|(_reg_86)) \r
- r_init_cnt <= ((_reg_176) ?_net_69:14'b0)|\r
- ((_reg_149) ?_net_66:14'b0)|\r
- ((_net_120) ?_net_57:14'b0)|\r
- ((_reg_93) ?_net_60:14'b0)|\r
- ((_net_192|_net_165|_net_129|_reg_98|_reg_91) ?14'b00000000000000:14'b0)|\r
- ((_reg_86) ?_net_63:14'b0);\r
+else if ((_reg_92)|(_reg_90)) \r
+ r_init_cnt <= ((_reg_92) ?14'b00000000000000:14'b0)|\r
+ ((_reg_90) ?_net_80:14'b0);\r
\r
end\r
-always @(posedge m_clock or posedge p_reset)\r
- begin\r
+always @(posedge p_reset)\r
+ begin\r
if (p_reset)\r
r_vram_adrs1 <= 14'b00000000000000;\r
-else if ((_net_156)|(_reg_149|_reg_93)) \r
- r_vram_adrs1 <= ((_net_156) ?14'b00000000000000:14'b0)|\r
- ((_reg_149|_reg_93) ?(r_vram_adrs1)+(14'b00000000000001):14'b0);\r
-\r
end\r
-always @(posedge m_clock or posedge p_reset)\r
- begin\r
+always @(posedge p_reset)\r
+ begin\r
if (p_reset)\r
r_vram_adrs2 <= 14'b00000000000000;\r
-else if ((_net_183)|(_reg_176|_reg_86)) \r
- r_vram_adrs2 <= ((_net_183) ?14'b00000000000000:14'b0)|\r
- ((_reg_176|_reg_86) ?(r_vram_adrs2)+(14'b00000000000001):14'b0);\r
-\r
end\r
-always @(posedge m_clock or posedge p_reset)\r
- begin\r
+always @(posedge p_reset)\r
+ begin\r
if (p_reset)\r
r_vram_rddata <= 16'b0000000000000000;\r
-else if ((_reg_179|_reg_152|_reg_96|_reg_89)) \r
- r_vram_rddata <= _u_EXP_o_Rdata;\r
end\r
-always @(posedge m_clock or posedge p_reset)\r
- begin\r
+always @(posedge p_reset)\r
+ begin\r
if (p_reset)\r
r_vram_start_adrs <= 14'b00000000000000;\r
-else if ((_net_202)|(_net_203|_reg_84)) \r
- r_vram_start_adrs <= ((_net_202) ?14'b00000000000000:14'b0)|\r
- ((_net_203|_reg_84) ?(r_vram_start_adrs)+(14'b00000000101000):14'b0);\r
-\r
end\r
always @(posedge m_clock or posedge p_reset)\r
begin\r
always @(posedge m_clock or posedge p_reset)\r
begin\r
if (p_reset)\r
- r_wradrs1 <= 8'b00000000;\r
-else if ((_reg_151|_reg_150|_reg_95|_reg_94)|(_reg_148|_reg_92)) \r
- r_wradrs1 <= ((_reg_151|_reg_150|_reg_95|_reg_94) ?(r_wradrs1)+(8'b00000001):8'b0)|\r
- ((_reg_148|_reg_92) ?8'b00000000:8'b0);\r
+ r_fifo_rst <= 1'b0;\r
+else if ((_net_109)|(_reg_96)) \r
+ r_fifo_rst <= ((_net_109) ?1'b1:1'b0)|\r
+ ((_reg_96) ?1'b0:1'b0);\r
\r
end\r
+always @(posedge p_reset)\r
+ begin\r
+if (p_reset)\r
+ r_wradrs1 <= 8'b00000000;\r
+end\r
+always @(posedge p_reset)\r
+ begin\r
+if (p_reset)\r
+ r_wradrs2 <= 8'b00000000;\r
+end\r
always @(posedge m_clock or posedge p_reset)\r
begin\r
if (p_reset)\r
- r_wradrs2 <= 8'b00000000;\r
-else if ((_reg_178|_reg_177|_reg_88|_reg_87)|(_reg_175|_reg_85)) \r
- r_wradrs2 <= ((_reg_178|_reg_177|_reg_88|_reg_87) ?(r_wradrs2)+(8'b00000001):8'b0)|\r
- ((_reg_175|_reg_85) ?8'b00000000:8'b0);\r
-\r
+ r_out_sel <= 1'b0;\r
+else if ((_u_BTN_fo_sw_enb)) \r
+ r_out_sel <= ~r_out_sel;\r
end\r
always @(posedge m_clock or posedge p_reset)\r
begin\r
if (p_reset)\r
r_wait_cnt <= 26'b00000000000000000000000000;\r
-else if ((_net_207)|(_net_205)) \r
- r_wait_cnt <= ((_net_207) ?(r_wait_cnt)+(26'b00000000000000000000000001):26'b0)|\r
- ((_net_205) ?26'b00000000000000000000000000:26'b0);\r
+else if ((_net_124)|(_net_122)) \r
+ r_wait_cnt <= ((_net_124) ?(r_wait_cnt)+(26'b00000000000000000000000001):26'b0)|\r
+ ((_net_122) ?26'b00000000000000000000000000:26'b0);\r
\r
end\r
always @(posedge p_reset)\r
begin\r
if (p_reset)\r
p_wait <= 1'b0;\r
-else if ((_net_70)) \r
+else if ((_net_81)) \r
p_wait <= _proc_p_wait_set;\r
end\r
always @(posedge m_clock or posedge p_reset)\r
begin\r
if (p_reset)\r
- _reg_83 <= 1'b0;\r
-else if ((_net_146)) \r
- _reg_83 <= _reg_84;\r
-end\r
-always @(posedge m_clock or posedge p_reset)\r
- begin\r
-if (p_reset)\r
- _reg_84 <= 1'b0;\r
-else if ((_net_145)) \r
- _reg_84 <= _reg_85;\r
-end\r
-always @(posedge m_clock or posedge p_reset)\r
- begin\r
-if (p_reset)\r
- _reg_85 <= 1'b0;\r
-else if ((_net_144)) \r
- _reg_85 <= _reg_85_goin|(_reg_86&(~_reg_86_goto));\r
-end\r
-always @(posedge m_clock or posedge p_reset)\r
- begin\r
-if (p_reset)\r
- _reg_86 <= 1'b0;\r
-else if ((_net_143)) \r
- _reg_86 <= _reg_87;\r
-end\r
-always @(posedge m_clock or posedge p_reset)\r
- begin\r
-if (p_reset)\r
- _reg_87 <= 1'b0;\r
-else if ((_net_142)) \r
- _reg_87 <= _reg_88;\r
-end\r
-always @(posedge m_clock or posedge p_reset)\r
- begin\r
-if (p_reset)\r
- _reg_88 <= 1'b0;\r
-else if ((_net_141)) \r
- _reg_88 <= _reg_89;\r
-end\r
-always @(posedge m_clock or posedge p_reset)\r
- begin\r
-if (p_reset)\r
_reg_89 <= 1'b0;\r
-else if ((_net_140)) \r
- _reg_89 <= _reg_90&(~_reg_90_goto);\r
+else if ((_net_120)) \r
+ _reg_89 <= _reg_89_goin|(_reg_90&(~_reg_90_goto));\r
end\r
always @(posedge m_clock or posedge p_reset)\r
begin\r
if (p_reset)\r
_reg_90 <= 1'b0;\r
-else if ((_net_139)) \r
- _reg_90 <= _reg_90_goin|_reg_91;\r
+else if ((_net_119)) \r
+ _reg_90 <= _reg_91&(~_reg_91_goto);\r
end\r
always @(posedge m_clock or posedge p_reset)\r
begin\r
if (p_reset)\r
_reg_91 <= 1'b0;\r
-else if ((_net_138)) \r
- _reg_91 <= _reg_92;\r
+else if ((_net_118)) \r
+ _reg_91 <= _reg_91_goin|_reg_92;\r
end\r
always @(posedge m_clock or posedge p_reset)\r
begin\r
if (p_reset)\r
_reg_92 <= 1'b0;\r
-else if ((_net_137)) \r
- _reg_92 <= _reg_92_goin|(_reg_93&(~_reg_93_goto));\r
+else if ((_net_117)) \r
+ _reg_92 <= _reg_93;\r
end\r
always @(posedge m_clock or posedge p_reset)\r
begin\r
if (p_reset)\r
_reg_93 <= 1'b0;\r
-else if ((_net_136)) \r
+else if ((_net_116)) \r
_reg_93 <= _reg_94;\r
end\r
always @(posedge m_clock or posedge p_reset)\r
begin\r
if (p_reset)\r
_reg_94 <= 1'b0;\r
-else if ((_net_135)) \r
+else if ((_net_115)) \r
_reg_94 <= _reg_95;\r
end\r
always @(posedge m_clock or posedge p_reset)\r
begin\r
if (p_reset)\r
_reg_95 <= 1'b0;\r
-else if ((_net_134)) \r
+else if ((_net_114)) \r
_reg_95 <= _reg_96;\r
end\r
always @(posedge m_clock or posedge p_reset)\r
begin\r
if (p_reset)\r
_reg_96 <= 1'b0;\r
-else if ((_net_133)) \r
- _reg_96 <= _reg_97&(~_reg_97_goto);\r
+else if ((_net_113)) \r
+ _reg_96 <= _reg_97;\r
end\r
always @(posedge m_clock or posedge p_reset)\r
begin\r
if (p_reset)\r
_reg_97 <= 1'b0;\r
-else if ((_net_132)) \r
- _reg_97 <= _reg_97_goin|_reg_98;\r
+else if ((_net_112)) \r
+ _reg_97 <= _reg_98;\r
end\r
always @(posedge m_clock or posedge p_reset)\r
begin\r
if (p_reset)\r
_reg_98 <= 1'b0;\r
-else if ((_net_131)) \r
- _reg_98 <= _reg_98_goin|(_reg_99&(~_reg_99_goto));\r
+else if ((_net_111)) \r
+ _reg_98 <= _reg_99;\r
end\r
always @(posedge m_clock or posedge p_reset)\r
begin\r
if (p_reset)\r
_reg_99 <= 1'b0;\r
-else if ((_net_130)) \r
- _reg_99 <= (_reg_99_goin|_reg_100)|fs_init;\r
+else if ((_net_110)) \r
+ _reg_99 <= _reg_100|fs_init;\r
end\r
always @(posedge m_clock or posedge p_reset)\r
begin\r
else if ((_reg_100)) \r
_reg_100 <= 1'b0;\r
end\r
-always @(posedge m_clock or posedge p_reset)\r
- begin\r
-if (p_reset)\r
- _reg_147 <= 1'b0;\r
-else if ((_net_172)) \r
- _reg_147 <= _reg_148;\r
-end\r
-always @(posedge m_clock or posedge p_reset)\r
- begin\r
-if (p_reset)\r
- _reg_148 <= 1'b0;\r
-else if ((_net_171)) \r
- _reg_148 <= _reg_148_goin|(_reg_149&(~_reg_149_goto));\r
-end\r
-always @(posedge m_clock or posedge p_reset)\r
- begin\r
-if (p_reset)\r
- _reg_149 <= 1'b0;\r
-else if ((_net_170)) \r
- _reg_149 <= _reg_150;\r
-end\r
-always @(posedge m_clock or posedge p_reset)\r
- begin\r
-if (p_reset)\r
- _reg_150 <= 1'b0;\r
-else if ((_net_169)) \r
- _reg_150 <= _reg_151;\r
-end\r
-always @(posedge m_clock or posedge p_reset)\r
- begin\r
-if (p_reset)\r
- _reg_151 <= 1'b0;\r
-else if ((_net_168)) \r
- _reg_151 <= _reg_152;\r
-end\r
-always @(posedge m_clock or posedge p_reset)\r
- begin\r
-if (p_reset)\r
- _reg_152 <= 1'b0;\r
-else if ((_net_167)) \r
- _reg_152 <= _reg_153&(~_reg_153_goto);\r
-end\r
-always @(posedge m_clock or posedge p_reset)\r
- begin\r
-if (p_reset)\r
- _reg_153 <= 1'b0;\r
-else if ((_net_166)) \r
- _reg_153 <= (_reg_153_goin|_reg_154)|fs_fifo1_charge;\r
-end\r
-always @(posedge m_clock or posedge p_reset)\r
- begin\r
-if (p_reset)\r
- _reg_154 <= 1'b0;\r
-else if ((_reg_154)) \r
- _reg_154 <= 1'b0;\r
-end\r
-always @(posedge m_clock or posedge p_reset)\r
- begin\r
-if (p_reset)\r
- _reg_173 <= 1'b0;\r
-else if ((_net_200)) \r
- _reg_173 <= _reg_174;\r
-end\r
-always @(posedge m_clock or posedge p_reset)\r
- begin\r
-if (p_reset)\r
- _reg_174 <= 1'b0;\r
-else if ((_net_199)) \r
- _reg_174 <= _reg_175;\r
-end\r
-always @(posedge m_clock or posedge p_reset)\r
- begin\r
-if (p_reset)\r
- _reg_175 <= 1'b0;\r
-else if ((_net_198)) \r
- _reg_175 <= _reg_175_goin|(_reg_176&(~_reg_176_goto));\r
-end\r
-always @(posedge m_clock or posedge p_reset)\r
- begin\r
-if (p_reset)\r
- _reg_176 <= 1'b0;\r
-else if ((_net_197)) \r
- _reg_176 <= _reg_177;\r
-end\r
-always @(posedge m_clock or posedge p_reset)\r
- begin\r
-if (p_reset)\r
- _reg_177 <= 1'b0;\r
-else if ((_net_196)) \r
- _reg_177 <= _reg_178;\r
-end\r
-always @(posedge m_clock or posedge p_reset)\r
- begin\r
-if (p_reset)\r
- _reg_178 <= 1'b0;\r
-else if ((_net_195)) \r
- _reg_178 <= _reg_179;\r
-end\r
-always @(posedge m_clock or posedge p_reset)\r
- begin\r
-if (p_reset)\r
- _reg_179 <= 1'b0;\r
-else if ((_net_194)) \r
- _reg_179 <= _reg_180&(~_reg_180_goto);\r
-end\r
-always @(posedge m_clock or posedge p_reset)\r
- begin\r
-if (p_reset)\r
- _reg_180 <= 1'b0;\r
-else if ((_net_193)) \r
- _reg_180 <= (_reg_180_goin|_reg_181)|fs_fifo2_charge;\r
-end\r
-always @(posedge m_clock or posedge p_reset)\r
- begin\r
-if (p_reset)\r
- _reg_181 <= 1'b0;\r
-else if ((_reg_181)) \r
- _reg_181 <= 1'b0;\r
-end\r
endmodule\r
/*\r
- Produced by NSL Core(version=20110302), IP ARCH, Inc. Wed Sep 21 22:08:07 2011\r
- Licensed to Yujiro_Kaneko::zyangalianhamster01@gmail.com \r
+ Produced by NSL Core(version=20110302), IP ARCH, Inc. Sun Nov 06 16:37:35 2011\r
+ Licensed to Yujiro_Kaneko::yujiro.kaneko@overtone.co.jp \r
*/\r
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