clk: msm: mdss: fix dp_link_2x_clk_mux clock ops for DP PLL on msmcobalt

The DP link clock path in the DSI PLL has a mux clock (dp_link_2x_clk_mux)
which allows the pixel clock to be either sourced out two divider clocks.
In the current code, the ops for this mux clock is overloaded
incorrectly which results in the link clock being always sourced
out of the first divider clock. Fix this by using
the default mux clock ops for this clock.

CRs-Fixed: 1009740
Change-Id: Ie12d5ab272dbd79fe97225864c2360fdde7325a7
Signed-off-by: Chandan Uddaraju <chandanu@codeaurora.org>

diff --git a/drivers/clk/msm/mdss/mdss-dp-pll-cobalt.c b/drivers/clk/msm/mdss/mdss-dp-pll-cobalt.c
index 1465ea1..c465dab 100644 (file)
--- a/drivers/clk/msm/mdss/mdss-dp-pll-cobalt.c
+++ b/drivers/clk/msm/mdss/mdss-dp-pll-cobalt.c
@@ -68,7 +68,6 @@ v----------+----------v         |     divsel_five     |    |     divsel_ten      |
 #include "mdss-dp-pll.h"
 #include "mdss-dp-pll-cobalt.h"
 
-static struct clk_ops clk_ops_gen_mux_dp;
 static struct clk_ops clk_ops_hsclk_divsel_clk_src_c;
 static struct clk_ops clk_ops_vco_divided_clk_src_c;
 static struct clk_ops clk_ops_link_2x_clk_div_c;
@@ -169,7 +168,7 @@ static struct mux_clk dp_link_2x_clk_mux = {
        .c = {
                .parent = &dp_link_2x_clk_divsel_five.c,
                .dbg_name = "dp_link_2x_clk_mux",
-               .ops = &clk_ops_gen_mux_dp,
+               .ops = &clk_ops_gen_mux,
                .flags = CLKFLAG_NO_RATE_CACHE,
                CLK_INIT(dp_link_2x_clk_mux.c),
        }
@@ -218,10 +217,6 @@ int dp_pll_clock_register_cobalt(struct platform_device *pdev,
        dp_link_2x_clk_divsel_five.priv = pll_res;
        dp_link_2x_clk_divsel_ten.priv = pll_res;
 
-       clk_ops_gen_mux_dp = clk_ops_gen_mux;
-       clk_ops_gen_mux_dp.round_rate = parent_round_rate;
-       clk_ops_gen_mux_dp.set_rate = parent_set_rate;
-
        clk_ops_hsclk_divsel_clk_src_c = clk_ops_div;
        clk_ops_hsclk_divsel_clk_src_c.prepare = mdss_pll_div_prepare;