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drm/amd/powerplay: avoid calling SMU7 specific SMU message implemention
authorEvan Quan <evan.quan@amd.com>
Thu, 26 Mar 2020 08:30:52 +0000 (16:30 +0800)
committerAlex Deucher <alexander.deucher@amd.com>
Wed, 1 Apr 2020 18:44:44 +0000 (14:44 -0400)
Prepare for coming lock protection for SMU message issuing.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
drivers/gpu/drm/amd/powerplay/hwmgr/smu7_thermal.c
drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c
drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c
drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c
drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c
drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.h
drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c
drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c

index 7740488..fc4e6dd 100644 (file)
@@ -3496,7 +3496,7 @@ static int smu7_get_gpu_power(struct pp_hwmgr *hwmgr, u32 *query)
            (adev->asic_type != CHIP_FIJI) &&
            (adev->asic_type != CHIP_TONGA)) {
                smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_GetCurrPkgPwr, 0);
-               tmp = cgs_read_register(hwmgr->device, mmSMC_MSG_ARG_0);
+               tmp = smum_get_argument(hwmgr);
                *query = tmp;
 
                if (tmp != 0)
@@ -3535,13 +3535,13 @@ static int smu7_read_sensor(struct pp_hwmgr *hwmgr, int idx,
        switch (idx) {
        case AMDGPU_PP_SENSOR_GFX_SCLK:
                smum_send_msg_to_smc(hwmgr, PPSMC_MSG_API_GetSclkFrequency);
-               sclk = cgs_read_register(hwmgr->device, mmSMC_MSG_ARG_0);
+               sclk = smum_get_argument(hwmgr);
                *((uint32_t *)value) = sclk;
                *size = 4;
                return 0;
        case AMDGPU_PP_SENSOR_GFX_MCLK:
                smum_send_msg_to_smc(hwmgr, PPSMC_MSG_API_GetMclkFrequency);
-               mclk = cgs_read_register(hwmgr->device, mmSMC_MSG_ARG_0);
+               mclk = smum_get_argument(hwmgr);
                *((uint32_t *)value) = mclk;
                *size = 4;
                return 0;
@@ -4455,7 +4455,7 @@ static int smu7_print_clock_levels(struct pp_hwmgr *hwmgr,
        switch (type) {
        case PP_SCLK:
                smum_send_msg_to_smc(hwmgr, PPSMC_MSG_API_GetSclkFrequency);
-               clock = cgs_read_register(hwmgr->device, mmSMC_MSG_ARG_0);
+               clock = smum_get_argument(hwmgr);
 
                for (i = 0; i < sclk_table->count; i++) {
                        if (clock > sclk_table->dpm_levels[i].value)
@@ -4471,7 +4471,7 @@ static int smu7_print_clock_levels(struct pp_hwmgr *hwmgr,
                break;
        case PP_MCLK:
                smum_send_msg_to_smc(hwmgr, PPSMC_MSG_API_GetMclkFrequency);
-               clock = cgs_read_register(hwmgr->device, mmSMC_MSG_ARG_0);
+               clock = smum_get_argument(hwmgr);
 
                for (i = 0; i < mclk_table->count; i++) {
                        if (clock > mclk_table->dpm_levels[i].value)
index 5bdc0df..dd4f450 100644 (file)
@@ -151,8 +151,8 @@ int smu7_fan_ctrl_start_smc_fan_control(struct pp_hwmgr *hwmgr)
        int result;
 
        if (PP_CAP(PHM_PlatformCaps_ODFuzzyFanControlSupport)) {
-               cgs_write_register(hwmgr->device, mmSMC_MSG_ARG_0, FAN_CONTROL_FUZZY);
-               result = smum_send_msg_to_smc(hwmgr, PPSMC_StartFanControl);
+               result = smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_StartFanControl,
+                                       FAN_CONTROL_FUZZY);
 
                if (PP_CAP(PHM_PlatformCaps_FanSpeedInTableIsRPM))
                        hwmgr->hwmgr_func->set_max_fan_rpm_output(hwmgr,
@@ -164,8 +164,8 @@ int smu7_fan_ctrl_start_smc_fan_control(struct pp_hwmgr *hwmgr)
                                        advanceFanControlParameters.usMaxFanPWM);
 
        } else {
-               cgs_write_register(hwmgr->device, mmSMC_MSG_ARG_0, FAN_CONTROL_TABLE);
-               result = smum_send_msg_to_smc(hwmgr, PPSMC_StartFanControl);
+               result = smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_StartFanControl,
+                                       FAN_CONTROL_TABLE);
        }
 
        if (!result && hwmgr->thermal_controller.
index 32ebb38..ab35e46 100644 (file)
@@ -137,9 +137,7 @@ static int fiji_start_smu_in_protection_mode(struct pp_hwmgr *hwmgr)
        PHM_WAIT_VFPF_INDIRECT_FIELD(hwmgr, SMC_IND, RCU_UC_EVENTS,
                        INTERRUPTS_ENABLED, 1);
 
-       cgs_write_register(hwmgr->device, mmSMC_MSG_ARG_0, 0x20000);
-       cgs_write_register(hwmgr->device, mmSMC_MESSAGE_0, PPSMC_MSG_Test);
-       PHM_WAIT_FIELD_UNEQUAL(hwmgr, SMC_RESP_0, SMC_RESP, 0);
+       smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_Test, 0x20000);
 
        /* Wait for done bit to be set */
        PHM_WAIT_VFPF_INDIRECT_FIELD_UNEQUAL(hwmgr, SMC_IND,
@@ -203,7 +201,7 @@ static int fiji_start_avfs_btc(struct pp_hwmgr *hwmgr)
        struct smu7_smumgr *smu_data = (struct smu7_smumgr *)(hwmgr->smu_backend);
 
        if (0 != smu_data->avfs_btc_param) {
-               if (0 != smu7_send_msg_to_smc_with_parameter(hwmgr,
+               if (0 != smum_send_msg_to_smc_with_parameter(hwmgr,
                                PPSMC_MSG_PerformBtc, smu_data->avfs_btc_param)) {
                        pr_info("[AVFS][Fiji_PerformBtc] PerformBTC SMU msg failed");
                        result = -EINVAL;
@@ -2649,6 +2647,7 @@ const struct pp_smumgr_func fiji_smu_funcs = {
        .request_smu_load_specific_fw = NULL,
        .send_msg_to_smc = &smu7_send_msg_to_smc,
        .send_msg_to_smc_with_parameter = &smu7_send_msg_to_smc_with_parameter,
+       .get_argument = smu7_get_argument,
        .download_pptable_settings = NULL,
        .upload_pptable_settings = NULL,
        .update_smc_table = fiji_update_smc_table,
index 732005c..431ad2f 100644 (file)
@@ -2669,6 +2669,7 @@ const struct pp_smumgr_func iceland_smu_funcs = {
        .request_smu_load_specific_fw = &iceland_request_smu_load_specific_fw,
        .send_msg_to_smc = &smu7_send_msg_to_smc,
        .send_msg_to_smc_with_parameter = &smu7_send_msg_to_smc_with_parameter,
+       .get_argument = smu7_get_argument,
        .download_pptable_settings = NULL,
        .upload_pptable_settings = NULL,
        .get_offsetof = iceland_get_offsetof,
index 23c1201..aaf9fd8 100644 (file)
@@ -99,7 +99,7 @@ static int polaris10_perform_btc(struct pp_hwmgr *hwmgr)
        struct smu7_smumgr *smu_data = (struct smu7_smumgr *)(hwmgr->smu_backend);
 
        if (0 != smu_data->avfs_btc_param) {
-               if (0 != smu7_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_PerformBtc, smu_data->avfs_btc_param)) {
+               if (0 != smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_PerformBtc, smu_data->avfs_btc_param)) {
                        pr_info("[AVFS][SmuPolaris10_PerformBtc] PerformBTC SMU msg failed");
                        result = -1;
                }
@@ -2565,6 +2565,7 @@ const struct pp_smumgr_func polaris10_smu_funcs = {
        .request_smu_load_specific_fw = NULL,
        .send_msg_to_smc = smu7_send_msg_to_smc,
        .send_msg_to_smc_with_parameter = smu7_send_msg_to_smc_with_parameter,
+       .get_argument = smu7_get_argument,
        .download_pptable_settings = NULL,
        .upload_pptable_settings = NULL,
        .update_smc_table = polaris10_update_smc_table,
index 3f51d54..07460ac 100644 (file)
@@ -214,18 +214,14 @@ int smu7_send_msg_to_smc_with_parameter_without_waiting(struct pp_hwmgr *hwmgr,
        return smu7_send_msg_to_smc_without_waiting(hwmgr, msg);
 }
 
-int smu7_send_msg_to_smc_offset(struct pp_hwmgr *hwmgr)
+uint32_t smu7_get_argument(struct pp_hwmgr *hwmgr)
 {
-       cgs_write_register(hwmgr->device, mmSMC_MSG_ARG_0, 0x20000);
-
-       cgs_write_register(hwmgr->device, mmSMC_MESSAGE_0, PPSMC_MSG_Test);
-
-       PHM_WAIT_FIELD_UNEQUAL(hwmgr, SMC_RESP_0, SMC_RESP, 0);
-
-       if (1 != PHM_READ_FIELD(hwmgr->device, SMC_RESP_0, SMC_RESP))
-               pr_info("Failed to send Message.\n");
+       return cgs_read_register(hwmgr->device, mmSMC_MSG_ARG_0);
+}
 
-       return 0;
+int smu7_send_msg_to_smc_offset(struct pp_hwmgr *hwmgr)
+{
+       return smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_Test, 0x20000);
 }
 
 enum cgs_ucode_id smu7_convert_fw_type_to_cgs(uint32_t fw_type)
@@ -353,10 +349,10 @@ int smu7_request_smu_load_fw(struct pp_hwmgr *hwmgr)
 
        if (hwmgr->chip_id > CHIP_TOPAZ) { /* add support for Topaz */
                if (hwmgr->not_vf) {
-                       smu7_send_msg_to_smc_with_parameter(hwmgr,
+                       smum_send_msg_to_smc_with_parameter(hwmgr,
                                                PPSMC_MSG_SMU_DRAM_ADDR_HI,
                                                upper_32_bits(smu_data->smu_buffer.mc_addr));
-                       smu7_send_msg_to_smc_with_parameter(hwmgr,
+                       smum_send_msg_to_smc_with_parameter(hwmgr,
                                                PPSMC_MSG_SMU_DRAM_ADDR_LO,
                                                lower_32_bits(smu_data->smu_buffer.mc_addr));
                }
@@ -423,10 +419,10 @@ int smu7_request_smu_load_fw(struct pp_hwmgr *hwmgr)
        }
        memcpy_toio(smu_data->header_buffer.kaddr, smu_data->toc,
                    sizeof(struct SMU_DRAMData_TOC));
-       smu7_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_DRV_DRAM_ADDR_HI, upper_32_bits(smu_data->header_buffer.mc_addr));
-       smu7_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_DRV_DRAM_ADDR_LO, lower_32_bits(smu_data->header_buffer.mc_addr));
+       smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_DRV_DRAM_ADDR_HI, upper_32_bits(smu_data->header_buffer.mc_addr));
+       smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_DRV_DRAM_ADDR_LO, lower_32_bits(smu_data->header_buffer.mc_addr));
 
-       smu7_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_LoadUcodes, fw_to_load);
+       smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_LoadUcodes, fw_to_load);
 
        r = smu7_check_fw_load_finish(hwmgr, fw_to_load);
        if (!r)
index 01f0538..fe27f46 100644 (file)
@@ -65,6 +65,7 @@ int smu7_send_msg_to_smc_with_parameter(struct pp_hwmgr *hwmgr, uint16_t msg,
                                                uint32_t parameter);
 int smu7_send_msg_to_smc_with_parameter_without_waiting(struct pp_hwmgr *hwmgr,
                                                uint16_t msg, uint32_t parameter);
+uint32_t smu7_get_argument(struct pp_hwmgr *hwmgr);
 int smu7_send_msg_to_smc_offset(struct pp_hwmgr *hwmgr);
 
 enum cgs_ucode_id smu7_convert_fw_type_to_cgs(uint32_t fw_type);
index f19bac7..6317434 100644 (file)
@@ -3248,6 +3248,7 @@ const struct pp_smumgr_func tonga_smu_funcs = {
        .request_smu_load_specific_fw = NULL,
        .send_msg_to_smc = &smu7_send_msg_to_smc,
        .send_msg_to_smc_with_parameter = &smu7_send_msg_to_smc_with_parameter,
+       .get_argument = smu7_get_argument,
        .download_pptable_settings = NULL,
        .upload_pptable_settings = NULL,
        .update_smc_table = tonga_update_smc_table,
index b0e0d67..0f38d51 100644 (file)
@@ -2279,6 +2279,7 @@ const struct pp_smumgr_func vegam_smu_funcs = {
        .request_smu_load_specific_fw = NULL,
        .send_msg_to_smc = smu7_send_msg_to_smc,
        .send_msg_to_smc_with_parameter = smu7_send_msg_to_smc_with_parameter,
+       .get_argument = smu7_get_argument,
        .process_firmware_header = vegam_process_firmware_header,
        .is_dpm_running = vegam_is_dpm_running,
        .get_mac_definition = vegam_get_mac_definition,