+2001-01-06 Ben Elliston <bje@redhat.com>
+
+ * utils-gen.scm (gen-sfmt-enum-decl): Use @prefix@ and @PREFIX@
+ instead of @cpu@ and @CPU@ to generically prefix symbol names.
+ * sim-cpu.scm (-gen-sem-fn-table-entry): Likewise.
+ (-gen-semantic-fn-table): Likewise.
+ (-gen-scache-semantic-fn): Likewise.
+ (-gen-no-scache-semantic-fn): Likewise.
+ (cgen-read.c): Likewise.
+ (cgen-sem-switch.c): Likewise.
+ * desc-cpu.scm (cgen-desc.c): Use @arch@, not @prefix@, since this
+ is a filename prefix.
+ * sim-decode.scm (IDESC-TABLE-VAR): Use @prefix@, et al.
+ (-gen-decode-insn-globals): Likewise.
+ (-gen-idesc-decls): Likewise.
+ (cgen-decode.h): Likewise.
+ (cgen-decode.c): Likewise.
+ * sim.scm (gen-cpu-insn-enum-decl): Likewise.
+ (gen-cpu-insn-enum): Likewise.
+ (sim-finish!): Likewise.
+
2001-01-05 Johan Rydberg <jrydberg@opencores.org>
* openrisc.cpu: New file.
; Generate .c/.h versions of main elements of cpu description file.
-; Copyright (C) 2000 Red Hat, Inc.
+; Copyright (C) 2000, 2001 Red Hat, Inc.
; This file is part of CGEN.
; ISA support code.
#include \"ansidecl.h\"
#include \"bfd.h\"
#include \"symcat.h\"
-#include \"@prefix@-desc.h\"
-#include \"@prefix@-opc.h\"
+#include \"@arch@-desc.h\"
+#include \"@arch@-opc.h\"
#include \"opintl.h\"
#include \"libiberty.h\"
\n"
; CPU family related simulator generator, excluding decoding and model support.
-; Copyright (C) 2000 Red Hat, Inc.
+; Copyright (C) 2000, 2001 Red Hat, Inc.
; This file is part of CGEN.
; Notes:
(define (-gen-sem-fn-table-entry insn)
(string-list
" { "
- "@CPU@_INSN_"
+ "@PREFIX@_INSN_"
(string-upcase (gen-sym insn))
", "
- "SEM_FN_NAME (@cpu@," (-gen-sem-fn-name insn) ")"
+ "SEM_FN_NAME (@prefix@," (-gen-sem-fn-name insn) ")"
" },\n"
)
)
/* Add the semantic fns to IDESC_TABLE. */
void
-SEM_FN_NAME (@cpu@,init_idesc_table) (SIM_CPU *current_cpu)
+SEM_FN_NAME (@prefix@,init_idesc_table) (SIM_CPU *current_cpu)
{
IDESC *idesc_table = CPU_IDESC (current_cpu);
const struct sem_fn_desc *sf;
if (valid_p)
idesc_table[sf->index].sem_fast = sf->fn;
else
- idesc_table[sf->index].sem_fast = SEM_FN_NAME (@cpu@,x_invalid);
+ idesc_table[sf->index].sem_fast = SEM_FN_NAME (@prefix@,x_invalid);
#else
if (valid_p)
idesc_table[sf->index].sem_full = sf->fn;
else
- idesc_table[sf->index].sem_full = SEM_FN_NAME (@cpu@,x_invalid);
+ idesc_table[sf->index].sem_full = SEM_FN_NAME (@prefix@,x_invalid);
#endif
}
}
(string-list
"/* " (obj:name insn) ": " (insn-syntax insn) " */\n\n"
"static SEM_PC\n"
- "SEM_FN_NAME (@cpu@," (gen-sym insn) ")"
+ "SEM_FN_NAME (@prefix@," (gen-sym insn) ")"
(if (and parallel? (not (with-generic-write?)))
" (SIM_CPU *current_cpu, SEM_ARG sem_arg, PAREXEC *par_exec)\n"
" (SIM_CPU *current_cpu, SEM_ARG sem_arg)\n")
(string-list
"/* " (obj:name insn) ": " (insn-syntax insn) " */\n\n"
"static SEM_STATUS\n"
- "SEM_FN_NAME (@cpu@," (gen-sym insn) ")"
+ "SEM_FN_NAME (@prefix@," (gen-sym insn) ")"
(if (and parallel? (not (with-generic-write?)))
" (SIM_CPU *current_cpu, SEM_ARG sem_arg, PAREXEC *par_exec, CGEN_INSN_INT insn)\n"
" (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn)\n")
(lambda ()
(string-write-map (lambda (insn)
(string-append " { "
- "@CPU@_INSN_"
+ "@PREFIX@_INSN_"
(string-upcase (gen-sym insn))
", && case_read_READ_"
(string-upcase (gen-sym (insn-sfmt insn)))
(lambda ()
(string-write-map (lambda (insn)
(string-append " { "
- "@CPU@_INSN_"
+ "@PREFIX@_INSN_"
(string-upcase (gen-sym insn))
", && case_sem_INSN_"
(string-upcase (gen-sym insn))
; Decoder generation.
-; Copyright (C) 2000 Red Hat, Inc.
+; Copyright (C) 2000, 2001 Red Hat, Inc.
; This file is part of CGEN.
; Names of various global vars.
; Name of insn descriptor table var.
-(define IDESC-TABLE-VAR "@cpu@_insn_data")
+(define IDESC-TABLE-VAR "@prefix@_insn_data")
; Return decode entries for each insn.
; ??? At one point we generated one variable per instruction rather than one
teensy bit of cpu in the decoder. Moving it to malloc space is trivial
but won't be done until necessary (we don't currently support the runtime
addition of instructions nor an SMP machine with different cpus). */
-static IDESC " IDESC-TABLE-VAR "[@CPU@_INSN_MAX];
+static IDESC " IDESC-TABLE-VAR "[@PREFIX@_INSN_MAX];
/* Commas between elements are contained in the macros.
Some of these are conditionally compiled out. */
-static const struct insn_sem @cpu@_insn_sem[] =
+static const struct insn_sem @prefix@_insn_sem[] =
{\n"
(string-list-map
(if virtual?
(string-append "VIRTUAL_INSN_" (string-upcase name) ", ")
(string-append "@ARCH@_INSN_" (string-upcase name) ", "))
- "@CPU@_INSN_" (string-upcase name) ", "
- "@CPU@_" (-gen-fmt-enum (insn-sfmt insn))
+ (string-append "@PREFIX@_INSN_" (string-upcase name) ", ")
+ "@PREFIX@_" (-gen-fmt-enum (insn-sfmt insn))
(if (and (with-parallel?) (not (with-parallel-only?)))
(string-list
(if (insn-parallel? insn)
- (string-append ", @CPU@_INSN_PAR_"
+ (string-append ", @PREFIX@_INSN_PAR_"
(string-upcase name)
", "
(if (with-parallel-read?)
- "@CPU@_INSN_READ_"
- "@CPU@_INSN_WRITE_")
+ "@PREFIX@_INSN_READ_"
+ "@PREFIX@_INSN_WRITE_")
(string-upcase name))
", NOPAR, NOPAR "))
"")
"\
};
-static const struct insn_sem @cpu@_insn_sem_invalid = {
- VIRTUAL_INSN_X_INVALID, @CPU@_INSN_X_INVALID, @CPU@_SFMT_EMPTY"
+static const struct insn_sem @prefix@_insn_sem_invalid = {
+ VIRTUAL_INSN_X_INVALID, @PREFIX@_INSN_X_INVALID, @PREFIX@_SFMT_EMPTY"
(if (and (with-parallel?) (not (with-parallel-only?)))
", NOPAR, NOPAR"
"")
(define (-gen-idesc-decls)
(string-append "\
-extern const IDESC *@cpu@_decode (SIM_CPU *, IADDR,
+extern const IDESC *@prefix@_decode (SIM_CPU *, IADDR,
CGEN_INSN_INT,"
(if (adata-integral-insn? CURRENT-ARCH)
" CGEN_INSN_INT,\n"
"\n")
"\
ARGBUF *);
-extern void @cpu@_init_idesc_table (SIM_CPU *);
-extern void @cpu@_sem_init_idesc_table (SIM_CPU *);
-extern void @cpu@_semf_init_idesc_table (SIM_CPU *);
+extern void @prefix@_init_idesc_table (SIM_CPU *);
+extern void @prefix@_sem_init_idesc_table (SIM_CPU *);
+extern void @prefix@_semf_init_idesc_table (SIM_CPU *);
\n")
)
; Return definition of C function to initialize the IDESC table.
-; @cpu@_init_idesc_table is defined here as it depends on with-parallel?
+; @prefix@_init_idesc_table is defined here as it depends on with-parallel?
; and thus can't be defined in sim/common.
(define (-gen-idesc-init-fn)
/* Initialize the instruction descriptor table. */
void
-@cpu@_init_idesc_table (SIM_CPU *cpu)
+@prefix@_init_idesc_table (SIM_CPU *cpu)
{
IDESC *id,*tabend;
const struct insn_sem *t,*tend;
- int tabsize = @CPU@_INSN_MAX;
+ int tabsize = @PREFIX@_INSN_MAX;
IDESC *table = " IDESC-TABLE-VAR ";
memset (table, 0, tabsize * sizeof (IDESC));
/* First set all entries to the `invalid insn'. */
- t = & @cpu@_insn_sem_invalid;
+ t = & @prefix@_insn_sem_invalid;
for (id = table, tabend = table + tabsize; id < tabend; ++id)
init_idesc (cpu, id, t);
/* Now fill in the values for the chosen cpu. */
- for (t = @cpu@_insn_sem, tend = t + sizeof (@cpu@_insn_sem) / sizeof (*t);
+ for (t = @prefix@_insn_sem, tend = t + sizeof (@prefix@_insn_sem) / sizeof (*t);
t != tend; ++t)
{
init_idesc (cpu, & table[t->index], t);\n"
(define (-gen-decode-fn insn-list initial-bitnums lsb0?)
; Compute the initial DECODE-BITSIZE as the minimum of all insn lengths.
- ; The caller of @cpu@_decode must fetch and pass exactly this number of bits
+ ; The caller of @prefix@_decode must fetch and pass exactly this number of bits
; of the instruction.
; ??? Make this a parameter later but only if necessary.
/* Given an instruction, return a pointer to its IDESC entry. */
const IDESC *
-@cpu@_decode (SIM_CPU *current_cpu, IADDR pc,
+@prefix@_decode (SIM_CPU *current_cpu, IADDR pc,
CGEN_INSN_INT base_insn,"
(if (adata-integral-insn? CURRENT-ARCH)
" CGEN_INSN_INT entire_insn,\n"
ARGBUF *abuf)
{
/* Result of decoder. */
- @CPU@_INSN_TYPE itype;
+ @PREFIX@_INSN_TYPE itype;
{
CGEN_INSN_INT insn = base_insn;
(set-with-parallel?! (state-parallel-exec?))
(string-write
- (gen-copyright "Decode header for @cpu@."
+ (gen-copyright "Decode header for @prefix@."
CURRENT-COPYRIGHT CURRENT-PACKAGE)
"\
-#ifndef @CPU@_DECODE_H
-#define @CPU@_DECODE_H
+#ifndef @PREFIX@_DECODE_H
+#define @PREFIX@_DECODE_H
"
-gen-idesc-decls
(non-multi-insns (non-alias-insns (current-insn-list)))))
(lambda () (gen-sfmt-enum-decl (current-sfmt-list)))
gen-model-fn-decls
- "#endif /* @CPU@_DECODE_H */\n"
+ "#endif /* @PREFIX@_DECODE_H */\n"
)
)
\f
(rtl-c-config! #:rtl-cover-fns? #t)
(string-write
- (gen-copyright "Simulator instruction decoder for @cpu@."
+ (gen-copyright "Simulator instruction decoder for @prefix@."
CURRENT-COPYRIGHT CURRENT-PACKAGE)
"\
#define WANT_CPU @cpu@
; Simulator generator support routines.
-; Copyright (C) 2000 Red Hat, Inc.
+; Copyright (C) 2000, 2001 Red Hat, Inc.
; This file is part of CGEN.
; One goal of this file is to provide cover functions for all methods.
; Return the declaration of the cpu/insn enum.
(define (gen-cpu-insn-enum-decl cpu insn-list)
- (gen-enum-decl "@cpu@_insn_type"
+ (gen-enum-decl "@prefix@_insn_type"
"instructions in cpu family @cpu@"
- "@CPU@_INSN_"
+ "@PREFIX@_INSN_"
(append! (map (lambda (i)
(cons (obj:name i)
(cons '-
; cache efficiently (since the IDESC table is similarily collapsed).
(define (gen-cpu-insn-enum cpu insn)
- (string-upcase (string-append "@CPU@_INSN_" (gen-sym insn)))
+ (string-upcase (string-append "@PREFIX@_INSN_" (gen-sym insn)))
)
; Return C code to declare the machine data.
(define (sim-finish!)
; Add begin,chain,before,after,invalid handlers if not provided.
- ; The code generators should first look for x-foo-@cpu@, then for x-foo.
+ ; The code generators should first look for x-foo-@prefix@, then for x-foo.
; ??? This is good enough for the first pass. Will eventually need to use
; less C and more RTL.
`(VIRTUAL PBB (ISA ,all))
"--begin--" () () '(c-code VOID "\
{
-#if WITH_SCACHE_PBB_@CPU@
+#if WITH_SCACHE_PBB_@PREFIX@
#if defined DEFINE_SWITCH || defined FAST_P
/* In the switch case FAST_P is a constant, allowing several optimizations
in any called inline functions. */
- vpc = @cpu@_pbb_begin (current_cpu, FAST_P);
+ vpc = @prefix@_pbb_begin (current_cpu, FAST_P);
#else
#if 0 /* cgen engine can't handle dynamic fast/full switching yet. */
- vpc = @cpu@_pbb_begin (current_cpu, STATE_RUN_FAST_P (CPU_STATE (current_cpu)));
+ vpc = @prefix@_pbb_begin (current_cpu, STATE_RUN_FAST_P (CPU_STATE (current_cpu)));
#else
- vpc = @cpu@_pbb_begin (current_cpu, 0);
+ vpc = @prefix@_pbb_begin (current_cpu, 0);
#endif
#endif
#endif
`(VIRTUAL PBB (ISA ,all))
"--chain--" () () '(c-code VOID "\
{
-#if WITH_SCACHE_PBB_@CPU@
- vpc = @cpu@_pbb_chain (current_cpu, sem_arg);
+#if WITH_SCACHE_PBB_@PREFIX@
+ vpc = @prefix@_pbb_chain (current_cpu, sem_arg);
#ifdef DEFINE_SWITCH
BREAK (sem);
#endif
`(VIRTUAL PBB (ISA ,all))
"--cti-chain--" () () '(c-code VOID "\
{
-#if WITH_SCACHE_PBB_@CPU@
+#if WITH_SCACHE_PBB_@PREFIX@
#ifdef DEFINE_SWITCH
- vpc = @cpu@_pbb_cti_chain (current_cpu, sem_arg,
+ vpc = @prefix@_pbb_cti_chain (current_cpu, sem_arg,
pbb_br_type, pbb_br_npc);
BREAK (sem);
#else
/* FIXME: Allow provision of explicit ifmt spec in insn spec. */
- vpc = @cpu@_pbb_cti_chain (current_cpu, sem_arg,
+ vpc = @prefix@_pbb_cti_chain (current_cpu, sem_arg,
CPU_PBB_BR_TYPE (current_cpu),
CPU_PBB_BR_NPC (current_cpu));
#endif
`(VIRTUAL PBB (ISA ,all))
"--before--" () () '(c-code VOID "\
{
-#if WITH_SCACHE_PBB_@CPU@
- @cpu@_pbb_before (current_cpu, sem_arg);
+#if WITH_SCACHE_PBB_@PREFIX@
+ @prefix@_pbb_before (current_cpu, sem_arg);
#endif
}
") nil)
`(VIRTUAL PBB (ISA ,all))
"--after--" () () '(c-code VOID "\
{
-#if WITH_SCACHE_PBB_@CPU@
- @cpu@_pbb_after (current_cpu, sem_arg);
+#if WITH_SCACHE_PBB_@PREFIX@
+ @prefix@_pbb_after (current_cpu, sem_arg);
#endif
}
") nil)
; Application independent utilities for C/C++ code generation.
-; Copyright (C) 2000 Red Hat, Inc.
+; Copyright (C) 2000, 2001 Red Hat, Inc.
; This file is part of CGEN.
; See file COPYING.CGEN for details.
; Instruction format utilities.
(define (gen-sfmt-enum-decl sfmt-list)
- (gen-enum-decl "@cpu@_sfmt_type"
+ (gen-enum-decl "@prefix@_sfmt_type"
"semantic formats in cpu family @cpu@"
- "@CPU@_"
+ "@PREFIX@_"
(map (lambda (sfmt) (cons (obj:name sfmt) nil))
sfmt-list))
)
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