///
const TargetAsmInfo *TAI;
+ /// Target Register Information.
+ ///
+ const TargetRegisterInfo *TRI;
+
/// Name-mangler for global names.
///
Mangler *Mang;
/// printInlineAsm - This method formats and prints the specified machine
/// instruction that is an inline asm.
void printInlineAsm(const MachineInstr *MI) const;
+
+ /// printImplicitDef - This method prints the specified machine instruction
+ /// that is an implicit def.
+ virtual void printImplicitDef(const MachineInstr *MI) const;
/// printBasicBlockLabel - This method prints the label for the specified
/// MachineBasicBlock
LABEL = 2,
DECLARE = 3,
EXTRACT_SUBREG = 4,
- INSERT_SUBREG = 5
+ INSERT_SUBREG = 5,
+ IMPLICIT_DEF = 6
};
// Target independent implict values for use with subreg insert. All targets
#include "llvm/Target/TargetData.h"
#include "llvm/Target/TargetLowering.h"
#include "llvm/Target/TargetMachine.h"
+#include "llvm/Target/TargetRegisterInfo.h"
#include "llvm/ADT/SmallPtrSet.h"
#include <cerrno>
using namespace llvm;
char AsmPrinter::ID = 0;
AsmPrinter::AsmPrinter(std::ostream &o, TargetMachine &tm,
const TargetAsmInfo *T)
- : MachineFunctionPass((intptr_t)&ID), FunctionNumber(0), O(o), TM(tm), TAI(T),
+ : MachineFunctionPass((intptr_t)&ID), FunctionNumber(0), O(o),
+ TM(tm), TAI(T), TRI(tm.getRegisterInfo()),
IsInTextSection(false)
{}
O << "\n\t" << TAI->getInlineAsmEnd() << "\n";
}
+/// printImplicitDef - This method prints the specified machine instruction
+/// that is an implicit def.
+void AsmPrinter::printImplicitDef(const MachineInstr *MI) const {
+ O << "\t" << TAI->getCommentString() << " implicit-def: "
+ << TRI->getAsmName(MI->getOperand(0).getReg()) << "\n";
+}
+
/// printLabel - This method prints a local label used by debug and
/// exception handling tables.
void AsmPrinter::printLabel(const MachineInstr *MI) const {
assert(isNew && "Node emitted out of order - early");
}
-void ScheduleDAG::CreateVirtualRegisters(SDNode *Node,
- MachineInstr *MI,
+void ScheduleDAG::CreateVirtualRegisters(SDNode *Node, MachineInstr *MI,
const TargetInstrDesc &II,
DenseMap<SDOperand, unsigned> &VRBaseMap) {
for (unsigned i = 0; i < II.getNumDefs(); ++i) {
// Create the result registers for this node and add the result regs to
// the machine instruction.
if (VRBase == 0) {
- const TargetRegisterClass *RC = getInstrOperandRegClass(TRI, TII, II, i);
+ const TargetRegisterClass *RC;
+ if (Node->getTargetOpcode() == TargetInstrInfo::IMPLICIT_DEF)
+ // IMPLICIT_DEF can produce any type of result so its TargetInstrDesc
+ // does not include operand register class info.
+ RC = DAG.getTargetLoweringInfo().getRegClassFor(Node->getValueType(0));
+ else
+ RC = getInstrOperandRegClass(TRI, TII, II, i);
assert(RC && "Isn't a register operand!");
VRBase = MRI.createVirtualRegister(RC);
MI->addOperand(MachineOperand::CreateReg(VRBase, true));
return TAI->getInlineAsmLength(MI->getOperand(0).getSymbolName());
if (MI->getOpcode() == ARM::LABEL)
return 0;
+ if (MI->getOpcode() == TargetInstrInfo::IMPLICIT_DEF)
+ return 0;
assert(0 && "Unknown or unset size field for instr!");
break;
case ARMII::Size8Bytes: return 8; // Arm instruction x 2.
//===----------------------------------------------------------------------===//
// Miscellaneous Instructions.
//
-let isImplicitDef = 1 in
-def IMPLICIT_DEF_GPR :
-PseudoInst<(outs GPR:$rD), (ins pred:$p),
- "@ IMPLICIT_DEF_GPR $rD",
- [(set GPR:$rD, (undef))]>;
-
/// CONSTPOOL_ENTRY - This instruction represents a floating constant pool in
/// the function. The first operand is the ID# for this instruction, the second
// FP <-> GPR Copies. Int <-> FP Conversions.
//
-let isImplicitDef = 1 in {
-def IMPLICIT_DEF_SPR : PseudoInst<(outs SPR:$rD), (ins pred:$p),
- "@ IMPLICIT_DEF_SPR $rD",
- [(set SPR:$rD, (undef))]>;
-def IMPLICIT_DEF_DPR : PseudoInst<(outs DPR:$rD), (ins pred:$p),
- "@ IMPLICIT_DEF_DPR $rD",
- [(set DPR:$rD, (undef))]>;
-}
-
def FMRS : ASI<(outs GPR:$dst), (ins SPR:$src),
"fmrs", " $dst, $src",
[(set GPR:$dst, (bitconvert SPR:$src))]>;
case Alpha::ALTENT:
case Alpha::PCLABEL:
case Alpha::MEMLABEL:
- case Alpha::IDEF_I:
- case Alpha::IDEF_F32:
- case Alpha::IDEF_F64:
break; //skip these
}
}
//Pseudo ops for selection
-let isImplicitDef = 1 in {
-def IDEF_I : PseudoInstAlpha<(outs GPRC:$RA), (ins), ";#idef $RA",
- [(set GPRC:$RA, (undef))], s_pseudo>;
-def IDEF_F32 : PseudoInstAlpha<(outs F4RC:$RA), (ins), ";#idef $RA",
- [(set F4RC:$RA, (undef))], s_pseudo>;
-def IDEF_F64 : PseudoInstAlpha<(outs F8RC:$RA), (ins), ";#idef $RA",
- [(set F8RC:$RA, (undef))], s_pseudo>;
-}
-
def WTF : PseudoInstAlpha<(outs), (ins variable_ops), "#wtf", [], s_pseudo>;
let hasCtrlDep = 1, Defs = [R30], Uses = [R30] in {
case Alpha::ALTENT:
case Alpha::MEMLABEL:
case Alpha::PCLABEL:
- case Alpha::IDEF_I:
- case Alpha::IDEF_F32:
- case Alpha::IDEF_F64:
--count;
break;
case Alpha::BR:
// TODO: support postincrement (reg, imm9) loads+stores - this needs more
// tablegen support
-let isImplicitDef = 1 in {
-def IDEF : PseudoInstIA64<(outs variable_ops), (ins), "// IDEF">;
-
-def IDEF_GR_D : PseudoInstIA64_DAG<(outs GR:$reg), (ins), "// $reg = IDEF",
- [(set GR:$reg, (undef))]>;
-def IDEF_FP_D : PseudoInstIA64_DAG<(outs FP:$reg), (ins), "// $reg = IDEF",
- [(set FP:$reg, (undef))]>;
-def IDEF_PR_D : PseudoInstIA64_DAG<(outs PR:$reg), (ins), "// $reg = IDEF",
- [(set PR:$reg, (undef))]>;
-}
-
def IUSE : PseudoInstIA64<(outs), (ins variable_ops), "// IUSE">;
def ADJUSTCALLSTACKUP : PseudoInstIA64<(outs), (ins variable_ops),
"// ADJUSTCALLSTACKUP">;
[(callseq_end imm:$amt1, imm:$amt2)]>;
}
-let isImplicitDef = 1 in
-def IMPLICIT_DEF_CPURegs : PseudoInstMips<(outs CPURegs:$dst), (ins),
- "!IMPLICIT_DEF $dst",
- [(set CPURegs:$dst, (undef))]>;
-
// When handling PIC code the assembler needs .cpload and .cprestore
// directives. If the real instructions corresponding these directives
// are used, we have the same behavior, but get also a bunch of warnings
///
static unsigned getNumBytesForInstruction(MachineInstr *MI) {
switch (MI->getOpcode()) {
- case PPC::IMPLICIT_DEF_GPRC: // no asm emitted
- case PPC::IMPLICIT_DEF_G8RC: // no asm emitted
- case PPC::IMPLICIT_DEF_F4: // no asm emitted
- case PPC::IMPLICIT_DEF_F8: // no asm emitted
- case PPC::IMPLICIT_DEF_VRRC: // no asm emitted
- return 0;
case PPC::INLINEASM: { // Inline Asm: Variable size.
MachineFunction *MF = MI->getParent()->getParent();
const char *AsmStr = MI->getOperand(0).getSymbolName();
case TargetInstrInfo::LABEL:
MCE.emitLabel(MI.getOperand(0).getImm());
break;
- case PPC::IMPLICIT_DEF_GPRC:
- case PPC::IMPLICIT_DEF_G8RC:
- case PPC::IMPLICIT_DEF_F8:
- case PPC::IMPLICIT_DEF_F4:
- case PPC::IMPLICIT_DEF_VRRC:
- break; // pseudo opcode, no side effects
case PPC::MovePCtoLR:
case PPC::MovePCtoLR8:
assert(TM.getRelocationModel() == Reloc::PIC_);
//===----------------------------------------------------------------------===//
-// Pseudo instructions.
-//
-
-def IMPLICIT_DEF_G8RC : Pseudo<(outs G8RC:$rD), (ins),"; IMPLICIT_DEF_G8RC $rD",
- [(set G8RC:$rD, (undef))]>;
-
-
-//===----------------------------------------------------------------------===//
// Calls.
//
//===----------------------------------------------------------------------===//
// Instruction Definitions.
-def IMPLICIT_DEF_VRRC : Pseudo<(outs VRRC:$rD), (ins),"; IMPLICIT_DEF_VRRC $rD",
- [(set VRRC:$rD, (v4i32 (undef)))]>;
-
def DSS : DSS_Form<822, (outs),
(ins u5imm:$ZERO0, u5imm:$STRM,u5imm:$ZERO1,u5imm:$ZERO2),
"dss $STRM", LdStGeneral /*FIXME*/, []>;
def : Pat<(int_ppc_altivec_dststt G8RC:$rA, GPRC:$rB, imm:$STRM),
(DSTSTT64 1, imm:$STRM, (i64 G8RC:$rA), GPRC:$rB)>;
-// Undef.
-def : Pat<(v16i8 (undef)), (IMPLICIT_DEF_VRRC)>;
-def : Pat<(v8i16 (undef)), (IMPLICIT_DEF_VRRC)>;
-def : Pat<(v4f32 (undef)), (IMPLICIT_DEF_VRRC)>;
-
// Loads.
def : Pat<(v4i32 (load xoaddr:$src)), (LVX xoaddr:$src)>;
[(set GPRC:$result,
(PPCdynalloc GPRC:$negsize, iaddr:$fpsi))]>;
-let isImplicitDef = 1 in {
-def IMPLICIT_DEF_GPRC: Pseudo<(outs GPRC:$rD), (ins),
- "${:comment}IMPLICIT_DEF_GPRC $rD",
- [(set GPRC:$rD, (undef))]>;
-def IMPLICIT_DEF_F8 : Pseudo<(outs F8RC:$rD), (ins),
- "${:comment} IMPLICIT_DEF_F8 $rD",
- [(set F8RC:$rD, (undef))]>;
-def IMPLICIT_DEF_F4 : Pseudo<(outs F4RC:$rD), (ins),
- "${:comment} IMPLICIT_DEF_F4 $rD",
- [(set F4RC:$rD, (undef))]>;
-}
-
// SELECT_CC_* - Used to implement the SELECT_CC DAG operation. Expanded by the
// scheduler into a branch sequence.
let usesCustomDAGSchedInserter = 1, // Expanded by the scheduler.
[(callseq_end imm:$amt1, imm:$amt2)]>;
}
-let isImplicitDef = 1 in {
-def IMPLICIT_DEF_Int : Pseudo<(outs IntRegs:$dst), (ins),
- "!IMPLICIT_DEF $dst",
- [(set IntRegs:$dst, (undef))]>;
-def IMPLICIT_DEF_FP : Pseudo<(outs FPRegs:$dst), (ins), "!IMPLICIT_DEF $dst",
- [(set FPRegs:$dst, (undef))]>;
-def IMPLICIT_DEF_DFP : Pseudo<(outs DFPRegs:$dst), (ins), "!IMPLICIT_DEF $dst",
- [(set DFPRegs:$dst, (undef))]>;
-}
-
// FpMOVD/FpNEGD/FpABSD - These are lowered to single-precision ops by the
// fpmover pass.
let Predicates = [HasNoV9] in { // Only emit these in V8 mode.
let Namespace = "TargetInstrInfo";
let neverHasSideEffects = 1;
}
+def IMPLICIT_DEF : Instruction {
+ let OutOperandList = (ops unknown:$dst);
+ let InOperandList = (ops);
+ let AsmString = "";
+ let Namespace = "TargetInstrInfo";
+ let neverHasSideEffects = 1;
+}
//===----------------------------------------------------------------------===//
// AsmWriter - This class can be implemented by targets that need to customize
void X86ATTAsmPrinter::printOperand(const MachineInstr *MI, unsigned OpNo,
const char *Modifier, bool NotRIPRel) {
const MachineOperand &MO = MI->getOperand(OpNo);
- const TargetRegisterInfo &RI = *TM.getRegisterInfo();
switch (MO.getType()) {
case MachineOperand::MO_Register: {
assert(TargetRegisterInfo::isPhysicalRegister(MO.getReg()) &&
((strcmp(Modifier+6,"16") == 0) ? MVT::i16 : MVT::i8));
Reg = getX86SubSuperRegister(Reg, VT);
}
- for (const char *Name = RI.get(Reg).AsmName; *Name; ++Name)
+ for (const char *Name = TRI->getAsmName(Reg); *Name; ++Name)
O << (char)tolower(*Name);
return;
}
bool X86ATTAsmPrinter::printAsmMRegister(const MachineOperand &MO,
const char Mode) {
- const TargetRegisterInfo &RI = *TM.getRegisterInfo();
unsigned Reg = MO.getReg();
switch (Mode) {
default: return true; // Unknown mode.
}
O << '%';
- for (const char *Name = RI.get(Reg).AsmName; *Name; ++Name)
+ for (const char *Name = TRI->getAsmName(Reg); *Name; ++Name)
O << (char)tolower(*Name);
return false;
}
break;
case TargetInstrInfo::DECLARE:
case X86::DWARF_LOC:
- case X86::IMPLICIT_DEF_GR8:
- case X86::IMPLICIT_DEF_GR16:
- case X86::IMPLICIT_DEF_GR32:
- case X86::IMPLICIT_DEF_GR64:
- case X86::IMPLICIT_DEF_FR32:
- case X86::IMPLICIT_DEF_FR64:
- case X86::IMPLICIT_DEF_VR64:
- case X86::IMPLICIT_DEF_VR128:
case X86::FP_REG_KILL:
break;
case X86::MOVPC32r: {
// Instruction list...
//
-let isImplicitDef = 1 in
-def IMPLICIT_DEF_GR64 : I<0, Pseudo, (outs GR64:$dst), (ins),
- "#IMPLICIT_DEF $dst",
- [(set GR64:$dst, (undef))]>;
-
//===----------------------------------------------------------------------===//
// Call Instructions...
//
"#ADJCALLSTACKUP",
[(X86callseq_end imm:$amt1, imm:$amt2)]>;
}
-let isImplicitDef = 1 in {
-def IMPLICIT_DEF_GR8 : I<0, Pseudo, (outs GR8:$dst), (ins),
- "#IMPLICIT_DEF $dst",
- [(set GR8:$dst, (undef))]>;
-def IMPLICIT_DEF_GR16 : I<0, Pseudo, (outs GR16:$dst), (ins),
- "#IMPLICIT_DEF $dst",
- [(set GR16:$dst, (undef))]>;
-def IMPLICIT_DEF_GR32 : I<0, Pseudo, (outs GR32:$dst), (ins),
- "#IMPLICIT_DEF $dst",
- [(set GR32:$dst, (undef))]>;
-}
// Nop
let neverHasSideEffects = 1 in
//
//===----------------------------------------------------------------------===//
-// Some 'special' instructions
-let isImplicitDef = 1 in
-def IMPLICIT_DEF_VR64 : I<0, Pseudo, (outs VR64:$dst), (ins),
- "#IMPLICIT_DEF $dst",
- [(set VR64:$dst, (v8i8 (undef)))]>,
- Requires<[HasMMX]>;
-
-// 64-bit vector undef's.
-def : Pat<(v8i8 (undef)), (IMPLICIT_DEF_VR64)>;
-def : Pat<(v4i16 (undef)), (IMPLICIT_DEF_VR64)>;
-def : Pat<(v2i32 (undef)), (IMPLICIT_DEF_VR64)>;
-def : Pat<(v1i64 (undef)), (IMPLICIT_DEF_VR64)>;
-
//===----------------------------------------------------------------------===//
// MMX Pattern Fragments
//===----------------------------------------------------------------------===//
SDTCisVT<2, f32>, SDTCisPtrTy<3>]>>;
//===----------------------------------------------------------------------===//
-// SSE 'Special' Instructions
-//===----------------------------------------------------------------------===//
-
-let isImplicitDef = 1 in {
-def IMPLICIT_DEF_VR128 : I<0, Pseudo, (outs VR128:$dst), (ins),
- "#IMPLICIT_DEF $dst",
- [(set VR128:$dst, (v4f32 (undef)))]>,
- Requires<[HasSSE1]>;
-def IMPLICIT_DEF_FR32 : I<0, Pseudo, (outs FR32:$dst), (ins),
- "#IMPLICIT_DEF $dst",
- [(set FR32:$dst, (undef))]>, Requires<[HasSSE1]>;
-def IMPLICIT_DEF_FR64 : I<0, Pseudo, (outs FR64:$dst), (ins),
- "#IMPLICIT_DEF $dst",
- [(set FR64:$dst, (undef))]>, Requires<[HasSSE2]>;
-}
-
-//===----------------------------------------------------------------------===//
// SSE Complex Patterns
//===----------------------------------------------------------------------===//
// Non-Instruction Patterns
//===----------------------------------------------------------------------===//
-// 128-bit vector undef's.
-def : Pat<(v4f32 (undef)), (IMPLICIT_DEF_VR128)>, Requires<[HasSSE2]>;
-def : Pat<(v2f64 (undef)), (IMPLICIT_DEF_VR128)>, Requires<[HasSSE2]>;
-def : Pat<(v16i8 (undef)), (IMPLICIT_DEF_VR128)>, Requires<[HasSSE2]>;
-def : Pat<(v8i16 (undef)), (IMPLICIT_DEF_VR128)>, Requires<[HasSSE2]>;
-def : Pat<(v4i32 (undef)), (IMPLICIT_DEF_VR128)>, Requires<[HasSSE2]>;
-def : Pat<(v2i64 (undef)), (IMPLICIT_DEF_VR128)>, Requires<[HasSSE2]>;
-
// extload f32 -> f64. This matches load+fextend because we have a hack in
// the isel (PreprocessForFPConvert) that can introduce loads after dag combine.
// Since these loads aren't folded into the fextend, we have to match it
void X86IntelAsmPrinter::printOp(const MachineOperand &MO,
const char *Modifier) {
- const TargetRegisterInfo &RI = *TM.getRegisterInfo();
switch (MO.getType()) {
case MachineOperand::MO_Register: {
if (TargetRegisterInfo::isPhysicalRegister(MO.getReg())) {
((strcmp(Modifier,"subreg16") == 0) ? MVT::i16 :MVT::i8));
Reg = getX86SubSuperRegister(Reg, VT);
}
- O << RI.get(Reg).AsmName;
+ O << TRI->getAsmName(Reg);
} else
O << "reg" << MO.getReg();
return;
bool X86IntelAsmPrinter::printAsmMRegister(const MachineOperand &MO,
const char Mode) {
- const TargetRegisterInfo &RI = *TM.getRegisterInfo();
unsigned Reg = MO.getReg();
switch (Mode) {
default: return true; // Unknown mode.
break;
}
- O << '%' << RI.get(Reg).AsmName;
+ O << '%' << TRI->getAsmName(Reg);
return false;
}
<< " } else if (MI->getOpcode() == TargetInstrInfo::DECLARE) {\n"
<< " printDeclare(MI);\n"
<< " return true;\n"
+ << " } else if (MI->getOpcode() == TargetInstrInfo::IMPLICIT_DEF) {\n"
+ << " printImplicitDef(MI);\n"
+ << " return true;\n"
<< " }\n\n";
O << " O << \"\\t\";\n\n";
R->getName() == "LABEL" ||
R->getName() == "DECLARE" ||
R->getName() == "EXTRACT_SUBREG" ||
- R->getName() == "INSERT_SUBREG") continue;
+ R->getName() == "INSERT_SUBREG" ||
+ R->getName() == "IMPLICIT_DEF") continue;
BitsInit *BI = R->getValueAsBitsInit("Inst");
R->getName() == "LABEL" ||
R->getName() == "DECLARE" ||
R->getName() == "EXTRACT_SUBREG" ||
- R->getName() == "INSERT_SUBREG") {
+ R->getName() == "INSERT_SUBREG" ||
+ R->getName() == "IMPLICIT_DEF") {
o << " 0U";
continue;
}
InstName == "LABEL"||
InstName == "DECLARE"||
InstName == "EXTRACT_SUBREG" ||
- InstName == "INSERT_SUBREG") continue;
+ InstName == "INSERT_SUBREG" ||
+ InstName == "IMPLICIT_DEF") continue;
BitsInit *BI = R->getValueAsBitsInit("Inst");
const std::vector<RecordVal> &Vals = R->getValues();
throw "Could not find 'INSERT_SUBREG' instruction!";
const CodeGenInstruction *INSERT_SUBREG = &I->second;
+ I = getInstructions().find("IMPLICIT_DEF");
+ if (I == Instructions.end())
+ throw "Could not find 'IMPLICIT_DEF' instruction!";
+ const CodeGenInstruction *IMPLICIT_DEF = &I->second;
+
// Print out the rest of the instructions now.
NumberedInstructions.push_back(PHI);
NumberedInstructions.push_back(INLINEASM);
NumberedInstructions.push_back(DECLARE);
NumberedInstructions.push_back(EXTRACT_SUBREG);
NumberedInstructions.push_back(INSERT_SUBREG);
+ NumberedInstructions.push_back(IMPLICIT_DEF);
for (inst_iterator II = inst_begin(), E = inst_end(); II != E; ++II)
if (&II->second != PHI &&
&II->second != INLINEASM &&
&II->second != LABEL &&
&II->second != DECLARE &&
&II->second != EXTRACT_SUBREG &&
- &II->second != INSERT_SUBREG)
+ &II->second != INSERT_SUBREG &&
+ &II->second != IMPLICIT_DEF)
NumberedInstructions.push_back(&II->second);
}
"Ops.size());\n"
<< " return New.Val;\n"
<< "}\n\n";
-
+
+ OS << "SDNode *Select_UNDEF(const SDOperand &N) {\n"
+ << " return CurDAG->getTargetNode(TargetInstrInfo::IMPLICIT_DEF,\n"
+ << " N.getValueType());\n"
+ << "}\n\n";
+
OS << "SDNode *Select_LABEL(const SDOperand &N) {\n"
<< " SDOperand Chain = N.getOperand(0);\n"
<< " SDOperand N1 = N.getOperand(1);\n"
<< " case ISD::LABEL: return Select_LABEL(N);\n"
<< " case ISD::DECLARE: return Select_DECLARE(N);\n"
<< " case ISD::EXTRACT_SUBREG: return Select_EXTRACT_SUBREG(N);\n"
- << " case ISD::INSERT_SUBREG: return Select_INSERT_SUBREG(N);\n";
+ << " case ISD::INSERT_SUBREG: return Select_INSERT_SUBREG(N);\n"
+ << " case ISD::UNDEF: return Select_UNDEF(N);\n";
// Loop over all of the case statements, emiting a call to each method we
R->getName() != "LABEL" &&
R->getName() != "DECLARE" &&
R->getName() != "EXTRACT_SUBREG" &&
- R->getName() != "INSERT_SUBREG")
+ R->getName() != "INSERT_SUBREG" &&
+ R->getName() != "IMPLICIT_DEF")
throw R->getName() + " doesn't have a field named '" +
Val->getValue() + "'!";
return;
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