arm64: dts: renesas: r8a7796: Add OPPs table for cpu devices

Define OOP tables for all CPUs.
This allows CPUFreq to function.

Based in part on work by Hien Dang.

Signed-off-by: Dien Pham <dien.pham.ry@rvc.renesas.com>
Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Tested-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>

diff --git a/arch/arm64/boot/dts/renesas/r8a7796.dtsi b/arch/arm64/boot/dts/renesas/r8a7796.dtsi
index c5192d5..e06bde6 100644 (file)
--- a/arch/arm64/boot/dts/renesas/r8a7796.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a7796.dtsi
@@ -71,6 +71,8 @@
                        power-domains = <&sysc R8A7796_PD_CA57_CPU0>;
                        next-level-cache = <&L2_CA57>;
                        enable-method = "psci";
+                       clocks =<&cpg CPG_CORE R8A7796_CLK_Z>;
+                       operating-points-v2 = <&cluster0_opp>;
                };
 
                a57_1: cpu@1 {
@@ -80,6 +82,8 @@
                        power-domains = <&sysc R8A7796_PD_CA57_CPU1>;
                        next-level-cache = <&L2_CA57>;
                        enable-method = "psci";
+                       clocks =<&cpg CPG_CORE R8A7796_CLK_Z>;
+                       operating-points-v2 = <&cluster0_opp>;
                };
 
                a53_0: cpu@100 {
@@ -89,6 +93,8 @@
                        power-domains = <&sysc R8A7796_PD_CA53_CPU0>;
                        next-level-cache = <&L2_CA53>;
                        enable-method = "psci";
+                       clocks =<&cpg CPG_CORE R8A7796_CLK_Z2>;
+                       operating-points-v2 = <&cluster1_opp>;
                };
 
                a53_1: cpu@101 {
@@ -98,6 +104,8 @@
                        power-domains = <&sysc R8A7796_PD_CA53_CPU1>;
                        next-level-cache = <&L2_CA53>;
                        enable-method = "psci";
+                       clocks =<&cpg CPG_CORE R8A7796_CLK_Z2>;
+                       operating-points-v2 = <&cluster1_opp>;
                };
 
                a53_2: cpu@102 {
@@ -107,6 +115,8 @@
                        power-domains = <&sysc R8A7796_PD_CA53_CPU2>;
                        next-level-cache = <&L2_CA53>;
                        enable-method = "psci";
+                       clocks =<&cpg CPG_CORE R8A7796_CLK_Z2>;
+                       operating-points-v2 = <&cluster1_opp>;
                };
 
                a53_3: cpu@103 {
@@ -116,6 +126,8 @@
                        power-domains = <&sysc R8A7796_PD_CA53_CPU3>;
                        next-level-cache = <&L2_CA53>;
                        enable-method = "psci";
+                       clocks =<&cpg CPG_CORE R8A7796_CLK_Z2>;
+                       operating-points-v2 = <&cluster1_opp>;
                };
 
                L2_CA57: cache-controller-0 {
@@ -147,6 +159,56 @@
                clock-frequency = <0>;
        };
 
+       cluster0_opp: opp_table0 {
+               compatible = "operating-points-v2";
+               opp-shared;
+
+               opp-500000000 {
+                       opp-hz = /bits/ 64 <500000000>;
+                       opp-microvolt = <820000>;
+                       clock-latency-ns = <300000>;
+               };
+               opp-1000000000 {
+                       opp-hz = /bits/ 64 <1000000000>;
+                       opp-microvolt = <820000>;
+                       clock-latency-ns = <300000>;
+               };
+               opp-1500000000 {
+                       opp-hz = /bits/ 64 <1500000000>;
+                       opp-microvolt = <820000>;
+                       clock-latency-ns = <300000>;
+               };
+               opp-1600000000 {
+                       opp-hz = /bits/ 64 <1600000000>;
+                       opp-microvolt = <900000>;
+                       clock-latency-ns = <300000>;
+                       turbo-mode;
+               };
+               opp-1700000000 {
+                       opp-hz = /bits/ 64 <1700000000>;
+                       opp-microvolt = <900000>;
+                       clock-latency-ns = <300000>;
+                       turbo-mode;
+               };
+               opp-1800000000 {
+                       opp-hz = /bits/ 64 <1800000000>;
+                       opp-microvolt = <960000>;
+                       clock-latency-ns = <300000>;
+                       turbo-mode;
+               };
+       };
+
+       cluster1_opp: opp_table1 {
+               compatible = "operating-points-v2";
+               opp-shared;
+
+               opp-1200000000 {
+                       opp-hz = /bits/ 64 <1200000000>;
+                       opp-microvolt = <820000>;
+                       clock-latency-ns = <300000>;
+               };
+       };
+
        /* External PCIe clock - can be overridden by the board */
        pcie_bus_clk: pcie_bus {
                compatible = "fixed-clock";