update.

diff --git a/simulation/cpu/mos6502.vhd b/simulation/cpu/mos6502.vhd
index 9d3058a..957da32 100644 (file)
--- a/simulation/cpu/mos6502.vhd
+++ b/simulation/cpu/mos6502.vhd
@@ -160,7 +160,6 @@ begin
         ---micro code part.
         if (set_clk'event and set_clk = '1') then
             d_print("-");
-            ---one byte instruction decoding.
 
             case cur_status is
                 when reset0 => 
@@ -184,43 +183,16 @@ begin
                 when decode => 
                     null;
                     --operation impletemnted latter code.
-
---                    elsif instruction = conv_std_logic_vector(16#a2#, dsize) then
---                        cur_status <= exec0;
---                        d_print("   ldx 0");
---                        addr <= pc;
---                        pc <= pc + 1;
---                    elsif instruction = conv_std_logic_vector(16#4c#, dsize) then
-----                        cur_status <= jmp1;
-----                        d_print("   jmp 0");
-----                        addr <= pc;
-----                        pc <= pc + 1;
---                    else
---                        d_print("   unknown instruction. decode failure.");
---                        cur_status <= unknown_stat;
---                    end if;
-
---                when ldx1 => 
---                    d_print("   ldx 1");
---                when jmp1 => 
---                    d_print("   jmp 1");
---                    pc <= pc + 1;
---                    cur_status <= jmp2;
---                when jmp2 => 
---                    d_print("   jmp 2");
---                    pc <= pc + 1;
---                    cur_status <= fetch;
                 when others => 
                     cur_status <= unknown_stat;
                     assert false 
                         report ("unknow status") severity failure;
             end case;
 
-            ---instruction consists of aaabbbcc form.
             if cur_status = decode then
                 d_print("inst: " & conv_hex8(conv_integer(instruction)));
 
-                ---rest of single byte instruction.
+                ---single byte instruction.
                 single_inst := false;
 
                 if instruction = conv_std_logic_vector(16#8a#, dsize) then
@@ -299,6 +271,7 @@ begin
                     addr <= (others => 'Z');
                 else
 
+                    ---instruction consists of aaabbbcc form.
                     if instruction (1 downto 0) = "01" then
                         d_print("cc=01");