Merge drm/drm-next into drm-intel-gt-next

Matt needed some buddy allocator changes for landing DG2 small BAR
support patches.

Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>

diff --cc drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c
Simple merge

diff --cc drivers/gpu/drm/i915/gem/i915_gem_stolen.c
Simple merge

diff --cc drivers/gpu/drm/i915/gem/selftests/huge_pages.c
Simple merge

diff --cc drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c
Simple merge

diff --cc drivers/gpu/drm/i915/gt/intel_engine_cs.c
Simple merge

diff --cc drivers/gpu/drm/i915/gt/intel_gt.c
Simple merge

diff --cc drivers/gpu/drm/i915/gt/intel_gtt.c
Simple merge

diff --cc drivers/gpu/drm/i915/gt/intel_region_lmem.c
index 7f711c1,a04e0cf..fc00888
--- 1/drivers/gpu/drm/i915/gt/intel_region_lmem.c
--- 2/drivers/gpu/drm/i915/gt/intel_region_lmem.c
+++ b/drivers/gpu/drm/i915/gt/intel_region_lmem.c
@@@ -11,7 -12,62 +12,8 @@@
  #include "gem/i915_gem_region.h"
  #include "gem/i915_gem_ttm.h"
  #include "gt/intel_gt.h"
+ #include "gt/intel_gt_regs.h"
  
 -static int init_fake_lmem_bar(struct intel_memory_region *mem)
 -{
 -      struct drm_i915_private *i915 = mem->i915;
 -      struct i915_ggtt *ggtt = to_gt(i915)->ggtt;
 -      unsigned long n;
 -      int ret;
 -
 -      /* We want to 1:1 map the mappable aperture to our reserved region */
 -
 -      mem->fake_mappable.start = 0;
 -      mem->fake_mappable.size = resource_size(&mem->region);
 -      mem->fake_mappable.color = I915_COLOR_UNEVICTABLE;
 -
 -      ret = drm_mm_reserve_node(&ggtt->vm.mm, &mem->fake_mappable);
 -      if (ret)
 -              return ret;
 -
 -      mem->remap_addr = dma_map_resource(i915->drm.dev,
 -                                         mem->region.start,
 -                                         mem->fake_mappable.size,
 -                                         DMA_BIDIRECTIONAL,
 -                                         DMA_ATTR_FORCE_CONTIGUOUS);
 -      if (dma_mapping_error(i915->drm.dev, mem->remap_addr)) {
 -              drm_mm_remove_node(&mem->fake_mappable);
 -              return -EINVAL;
 -      }
 -
 -      for (n = 0; n < mem->fake_mappable.size >> PAGE_SHIFT; ++n) {
 -              ggtt->vm.insert_page(&ggtt->vm,
 -                                   mem->remap_addr + (n << PAGE_SHIFT),
 -                                   n << PAGE_SHIFT,
 -                                   I915_CACHE_NONE, 0);
 -      }
 -
 -      mem->region = (struct resource)DEFINE_RES_MEM(mem->remap_addr,
 -                                                    mem->fake_mappable.size);
 -
 -      return 0;
 -}
 -
 -static void release_fake_lmem_bar(struct intel_memory_region *mem)
 -{
 -      if (!drm_mm_node_allocated(&mem->fake_mappable))
 -              return;
 -
 -      drm_mm_remove_node(&mem->fake_mappable);
 -
 -      dma_unmap_resource(mem->i915->drm.dev,
 -                         mem->remap_addr,
 -                         mem->fake_mappable.size,
 -                         DMA_BIDIRECTIONAL,
 -                         DMA_ATTR_FORCE_CONTIGUOUS);
 -}
 -
  static int
  region_lmem_release(struct intel_memory_region *mem)
  {

diff --cc drivers/gpu/drm/i915/gt/intel_rps.c
Simple merge

diff --cc drivers/gpu/drm/i915/gt/intel_workarounds.c
Simple merge

diff --cc drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c
index 8df6bc8,b3d28b0..ac749ab
--- 1/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c
--- 2/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c
@@@ -3,10 -3,14 +3,15 @@@
   * Copyright © 2021 Intel Corporation
   */
  
+ #include <drm/drm_cache.h>
+ 
  #include "i915_drv.h"
+ #include "i915_reg.h"
  #include "intel_guc_slpc.h"
+ #include "intel_mchbar_regs.h"
  #include "gt/intel_gt.h"
+ #include "gt/intel_gt_regs.h"
 +#include "gt/intel_rps.h"
  
  static inline struct intel_guc *slpc_to_guc(struct intel_guc_slpc *slpc)
  {

diff --cc drivers/gpu/drm/i915/i915_driver.c
Simple merge

diff --cc drivers/gpu/drm/i915/i915_drv.h
Simple merge

diff --cc drivers/gpu/drm/i915/i915_pci.c
Simple merge

diff --cc drivers/gpu/drm/i915/i915_perf.c
Simple merge

diff --cc drivers/gpu/drm/i915/i915_reg.h
index 8d28d1e,2b8a308..cfd5696
--- 1/drivers/gpu/drm/i915/i915_reg.h
--- 2/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@@ -12645,24 -8460,12 +8460,26 @@@ enum skl_power_gate 
  #define   SGGI_DIS                    REG_BIT(15)
  #define   SGR_DIS                     REG_BIT(13)
  
 +#define XEHPSDV_FLAT_CCS_BASE_ADDR    _MMIO(0x4910)
 +#define   XEHPSDV_CCS_BASE_SHIFT      8
 +
 +/* gamt regs */
 +#define GEN8_L3_LRA_1_GPGPU _MMIO(0x4dd4)
 +#define   GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_BDW  0x67F1427F /* max/min for LRA1/2 */
 +#define   GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_CHV  0x5FF101FF /* max/min for LRA1/2 */
 +#define   GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_SKL  0x67F1427F /*    "        " */
 +#define   GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_BXT  0x5FF101FF /*    "        " */
 +
 +#define MMCD_MISC_CTRL                _MMIO(0x4ddc) /* skl+ */
 +#define  MMCD_PCLA            (1 << 31)
 +#define  MMCD_HOTSPOT_EN      (1 << 27)
 +
  #define _ICL_PHY_MISC_A               0x64C00
  #define _ICL_PHY_MISC_B               0x64C04
- #define ICL_PHY_MISC(port)    _MMIO_PORT(port, _ICL_PHY_MISC_A, \
-                                                _ICL_PHY_MISC_B)
+ #define _DG2_PHY_MISC_TC1     0x64C14 /* TC1="PHY E" but offset as if "PHY F" */
+ #define ICL_PHY_MISC(port)    _MMIO_PORT(port, _ICL_PHY_MISC_A, _ICL_PHY_MISC_B)
+ #define DG2_PHY_MISC(port)    ((port) == PHY_E ? _MMIO(_DG2_PHY_MISC_TC1) : \
+                                ICL_PHY_MISC(port))
  #define  ICL_PHY_MISC_MUX_DDID                        (1 << 28)
  #define  ICL_PHY_MISC_DE_IO_COMP_PWR_DOWN     (1 << 23)
  #define  DG2_PHY_DP_TX_ACK_MASK                       REG_GENMASK(23, 20)

diff --cc drivers/gpu/drm/i915/i915_vma.c
Simple merge

diff --cc drivers/gpu/drm/i915/intel_device_info.c
index 3a713b4,94da5aa..32c5f10
--- 1/drivers/gpu/drm/i915/intel_device_info.c
--- 2/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@@ -170,10 -170,10 +170,14 @@@ static const u16 subplatform_portf_ids[
        INTEL_ICL_PORT_F_IDS(0),
  };
  
 +static const u16 subplatform_uy_ids[] = {
 +      INTEL_TGL_12_GT2_IDS(0),
 +};
 +
+ static const u16 subplatform_n_ids[] = {
+       INTEL_ADLN_IDS(0),
+ };
+ 
  static const u16 subplatform_rpls_ids[] = {
        INTEL_RPLS_IDS(0),
  };
@@@ -214,9 -214,9 +218,12 @@@ void intel_device_info_subplatform_init
        } else if (find_devid(devid, subplatform_portf_ids,
                              ARRAY_SIZE(subplatform_portf_ids))) {
                mask = BIT(INTEL_SUBPLATFORM_PORTF);
 +      } else if (find_devid(devid, subplatform_uy_ids,
 +                         ARRAY_SIZE(subplatform_uy_ids))) {
 +              mask = BIT(INTEL_SUBPLATFORM_UY);
+       } else if (find_devid(devid, subplatform_n_ids,
+                               ARRAY_SIZE(subplatform_n_ids))) {
+               mask = BIT(INTEL_SUBPLATFORM_N);
        } else if (find_devid(devid, subplatform_rpls_ids,
                              ARRAY_SIZE(subplatform_rpls_ids))) {
                mask = BIT(INTEL_SUBPLATFORM_RPL_S);

diff --cc drivers/gpu/drm/i915/intel_device_info.h
Simple merge

diff --cc drivers/gpu/drm/i915/selftests/i915_gem_gtt.c
index ca4ed9d,e7e6c4b..ab75119
--- 1/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c
--- 2/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c
@@@ -26,7 -26,7 +26,8 @@@
  #include <linux/prime_numbers.h>
  
  #include "gem/i915_gem_context.h"
+ #include "gem/i915_gem_internal.h"
 +#include "gem/i915_gem_region.h"
  #include "gem/selftests/mock_context.h"
  #include "gt/intel_context.h"
  #include "gt/intel_gpu_commands.h"