drm/amd/pm: correct Polaris DIDT configurations

Correct Polaris DIDT enablement.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/pm/inc/smu7_ppsmc.h b/drivers/gpu/drm/amd/pm/inc/smu7_ppsmc.h
index 97302aa..a0a38b8 100644 (file)
--- a/drivers/gpu/drm/amd/pm/inc/smu7_ppsmc.h
+++ b/drivers/gpu/drm/amd/pm/inc/smu7_ppsmc.h
@@ -403,6 +403,8 @@ typedef uint16_t PPSMC_Result;
 
 #define PPSMC_MSG_EnableDpmDidt               ((uint16_t) 0x309)
 #define PPSMC_MSG_DisableDpmDidt              ((uint16_t) 0x30A)
+#define PPSMC_MSG_EnableDpmMcBlackout         ((uint16_t) 0x30B)
+#define PPSMC_MSG_DisableDpmMcBlackout        ((uint16_t) 0x30C)
 
 #define PPSMC_MSG_EnableEDCController         ((uint16_t) 0x316)
 #define PPSMC_MSG_DisableEDCController        ((uint16_t) 0x317)

diff --git a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_powertune.c b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_powertune.c
index 5d49715..32a5a00 100644 (file)
--- a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_powertune.c
+++ b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_powertune.c
@@ -852,12 +852,14 @@ static const struct gpu_pt_config_reg DIDTConfig_VegaM[] =
 };
 static int smu7_enable_didt(struct pp_hwmgr *hwmgr, const bool enable)
 {
+       struct amdgpu_device *adev = hwmgr->adev;
        uint32_t en = enable ? 1 : 0;
        uint32_t block_en = 0;
        int32_t result = 0;
        uint32_t didt_block;
 
-       if (hwmgr->chip_id == CHIP_POLARIS11)
+       if ((hwmgr->chip_id == CHIP_POLARIS11) &&
+           (adev->pdev->subsystem_vendor != 0x106B))
                didt_block = Polaris11_DIDTBlock_Info;
        else
                didt_block = DIDTBlock_Info;
@@ -962,6 +964,7 @@ int smu7_enable_didt_config(struct pp_hwmgr *hwmgr)
        uint32_t num_se = 0;
        uint32_t count, value, value2;
        struct amdgpu_device *adev = hwmgr->adev;
+       uint32_t efuse;
 
        num_se = adev->gfx.config.max_shader_engines;
 
@@ -988,7 +991,9 @@ int smu7_enable_didt_config(struct pp_hwmgr *hwmgr)
                        } else if (hwmgr->chip_id == CHIP_POLARIS11) {
                                result = smu7_program_pt_config_registers(hwmgr, GCCACConfig_Polaris11);
                                PP_ASSERT_WITH_CODE((result == 0), "DIDT Config failed.", goto error);
-                               if (hwmgr->is_kicker)
+
+                               if (ASICID_IS_P21(adev->pdev->device, adev->pdev->revision) ||
+                                   ASICID_IS_P31(adev->pdev->device, adev->pdev->revision))
                                        result = smu7_program_pt_config_registers(hwmgr, DIDTConfig_Polaris11_Kicker);
                                else
                                        result = smu7_program_pt_config_registers(hwmgr, DIDTConfig_Polaris11);
@@ -1016,7 +1021,32 @@ int smu7_enable_didt_config(struct pp_hwmgr *hwmgr)
                                                NULL);
                        PP_ASSERT_WITH_CODE((0 == result),
                                        "Failed to enable DPM DIDT.", goto error);
+
+                       if (ASICID_IS_P21(adev->pdev->device, adev->pdev->revision) ||
+                           ASICID_IS_P31(adev->pdev->device, adev->pdev->revision)) {
+                               result = smum_send_msg_to_smc(hwmgr,
+                                                       (uint16_t)(PPSMC_MSG_EnableDpmMcBlackout),
+                                                       NULL);
+                               PP_ASSERT_WITH_CODE((0 == result),
+                                               "Failed to enable workaround for CRC issue.", goto error);
+                       } else {
+                               atomctrl_read_efuse(hwmgr, 547, 547, &efuse);
+                               if (efuse == 1) {
+                                       result = smum_send_msg_to_smc(hwmgr,
+                                                               (uint16_t)(PPSMC_MSG_EnableDpmMcBlackout),
+                                                               NULL);
+                                       PP_ASSERT_WITH_CODE((0 == result),
+                                                       "Failed to enable workaround for CRC issue.", goto error);
+                               } else {
+                                       result = smum_send_msg_to_smc(hwmgr,
+                                                               (uint16_t)(PPSMC_MSG_DisableDpmMcBlackout),
+                                                               NULL);
+                                       PP_ASSERT_WITH_CODE((0 == result),
+                                                       "Failed to enable workaround for CRC issue.", goto error);
+                               }
+                       }
                }
+
                mutex_unlock(&adev->grbm_idx_mutex);
                amdgpu_gfx_rlc_exit_safe_mode(adev);
        }