let DecoderMethod = "DecodeSOImmOperand";
}
+// mod_imm: match a 32-bit immediate operand, which is encoded as a 12-bit
+// immediate (See ARMARM - "Modified Immediate Constants"). Unlike so_imm,
+// mod_imm keeps the immediate in its encoded form (within the MC layer).
+def ModImmAsmOperand: AsmOperandClass {
+ let Name = "ModImm";
+ let ParserMethod = "parseModImm";
+}
+def mod_imm : Operand<i32>, ImmLeaf<i32, [{
+ return ARM_AM::getSOImmVal(Imm) != -1;
+ }]> {
+ let EncoderMethod = "getModImmOpValue";
+ let PrintMethod = "printModImmOperand";
+ let ParserMatchClass = ModImmAsmOperand;
+}
+
+// similar to so_imm_not, but keeps the immediate in its encoded form
+def ModImmNotAsmOperand : AsmOperandClass { let Name = "ModImmNot"; }
+def mod_imm_not : Operand<i32>, PatLeaf<(imm), [{
+ return ARM_AM::getSOImmVal(~(uint32_t)N->getZExtValue()) != -1;
+ }], imm_not_XFORM> {
+ let ParserMatchClass = ModImmNotAsmOperand;
+}
+
+// similar to so_imm_neg, but keeps the immediate in its encoded form
+def ModImmNegAsmOperand : AsmOperandClass { let Name = "ModImmNeg"; }
+def mod_imm_neg : Operand<i32>, PatLeaf<(imm), [{
+ unsigned Value = -(unsigned)N->getZExtValue();
+ return Value && ARM_AM::getSOImmVal(Value) != -1;
+ }], imm_neg_XFORM> {
+ let ParserMatchClass = ModImmNegAsmOperand;
+}
+
// Break so_imm's up into two pieces. This handles immediates with up to 16
// bits set in them. This uses so_imm2part to match and so_imm2part_[12] to
// get the first/second pieces.
// The register-immediate version is re-materializable. This is useful
// in particular for taking the address of a local.
let isReMaterializable = 1 in {
- def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm), DPFrm,
+ def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, mod_imm:$imm), DPFrm,
iii, opc, "\t$Rd, $Rn, $imm",
- [(set GPR:$Rd, (opnode GPR:$Rn, so_imm:$imm))]>,
+ [(set GPR:$Rd, (opnode GPR:$Rn, mod_imm:$imm))]>,
Sched<[WriteALU, ReadALU]> {
bits<4> Rd;
bits<4> Rn;
// The register-immediate version is re-materializable. This is useful
// in particular for taking the address of a local.
let isReMaterializable = 1 in {
- def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm), DPFrm,
+ def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, mod_imm:$imm), DPFrm,
iii, opc, "\t$Rd, $Rn, $imm",
- [(set GPR:$Rd, (opnode so_imm:$imm, GPR:$Rn))]>,
+ [(set GPR:$Rd, (opnode mod_imm:$imm, GPR:$Rn))]>,
Sched<[WriteALU, ReadALU]> {
bits<4> Rd;
bits<4> Rn;
multiclass AsI1_bin_s_irs<InstrItinClass iii, InstrItinClass iir,
InstrItinClass iis, PatFrag opnode,
bit Commutable = 0> {
- def ri : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm, pred:$p),
+ def ri : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, mod_imm:$imm, pred:$p),
4, iii,
- [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, so_imm:$imm))]>,
+ [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, mod_imm:$imm))]>,
Sched<[WriteALU, ReadALU]>;
def rr : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, pred:$p),
multiclass AsI1_rbin_s_is<InstrItinClass iii, InstrItinClass iir,
InstrItinClass iis, PatFrag opnode,
bit Commutable = 0> {
- def ri : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm, pred:$p),
+ def ri : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, mod_imm:$imm, pred:$p),
4, iii,
- [(set GPR:$Rd, CPSR, (opnode so_imm:$imm, GPR:$Rn))]>,
+ [(set GPR:$Rd, CPSR, (opnode mod_imm:$imm, GPR:$Rn))]>,
Sched<[WriteALU, ReadALU]>;
def rsi : ARMPseudoInst<(outs GPR:$Rd),
multiclass AI1_cmp_irs<bits<4> opcod, string opc,
InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
PatFrag opnode, bit Commutable = 0> {
- def ri : AI1<opcod, (outs), (ins GPR:$Rn, so_imm:$imm), DPFrm, iii,
+ def ri : AI1<opcod, (outs), (ins GPR:$Rn, mod_imm:$imm), DPFrm, iii,
opc, "\t$Rn, $imm",
- [(opnode GPR:$Rn, so_imm:$imm)]>,
+ [(opnode GPR:$Rn, mod_imm:$imm)]>,
Sched<[WriteCMP, ReadALU]> {
bits<4> Rn;
bits<12> imm;
multiclass AI1_adde_sube_irs<bits<4> opcod, string opc, PatFrag opnode,
bit Commutable = 0> {
let hasPostISelHook = 1, Defs = [CPSR], Uses = [CPSR] in {
- def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm),
+ def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, mod_imm:$imm),
DPFrm, IIC_iALUi, opc, "\t$Rd, $Rn, $imm",
- [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, so_imm:$imm, CPSR))]>,
+ [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, mod_imm:$imm, CPSR))]>,
Requires<[IsARM]>,
Sched<[WriteALU, ReadALU]> {
bits<4> Rd;
let TwoOperandAliasConstraint = "$Rn = $Rd" in
multiclass AI1_rsc_irs<bits<4> opcod, string opc, PatFrag opnode> {
let hasPostISelHook = 1, Defs = [CPSR], Uses = [CPSR] in {
- def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm),
+ def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, mod_imm:$imm),
DPFrm, IIC_iALUi, opc, "\t$Rd, $Rn, $imm",
- [(set GPR:$Rd, CPSR, (opnode so_imm:$imm, GPR:$Rn, CPSR))]>,
+ [(set GPR:$Rd, CPSR, (opnode mod_imm:$imm, GPR:$Rn, CPSR))]>,
Requires<[IsARM]>,
Sched<[WriteALU, ReadALU]> {
bits<4> Rd;
}
let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in
-def MOVi : AsI1<0b1101, (outs GPR:$Rd), (ins so_imm:$imm), DPFrm, IIC_iMOVi,
- "mov", "\t$Rd, $imm", [(set GPR:$Rd, so_imm:$imm)]>, UnaryDP,
+def MOVi : AsI1<0b1101, (outs GPR:$Rd), (ins mod_imm:$imm), DPFrm, IIC_iMOVi,
+ "mov", "\t$Rd, $imm", [(set GPR:$Rd, mod_imm:$imm)]>, UnaryDP,
Sched<[WriteALU]> {
bits<4> Rd;
bits<12> imm;
let Inst{3-0} = shift{3-0};
}
let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in
-def MVNi : AsI1<0b1111, (outs GPR:$Rd), (ins so_imm:$imm), DPFrm,
+def MVNi : AsI1<0b1111, (outs GPR:$Rd), (ins mod_imm:$imm), DPFrm,
IIC_iMVNi, "mvn", "\t$Rd, $imm",
- [(set GPR:$Rd, so_imm_not:$imm)]>,UnaryDP, Sched<[WriteALU]> {
+ [(set GPR:$Rd, mod_imm_not:$imm)]>,UnaryDP, Sched<[WriteALU]> {
bits<4> Rd;
bits<12> imm;
let Inst{25} = 1;
// CMN register-integer
let isCompare = 1, Defs = [CPSR] in {
-def CMNri : AI1<0b1011, (outs), (ins GPR:$Rn, so_imm:$imm), DPFrm, IIC_iCMPi,
+def CMNri : AI1<0b1011, (outs), (ins GPR:$Rn, mod_imm:$imm), DPFrm, IIC_iCMPi,
"cmn", "\t$Rn, $imm",
- [(ARMcmn GPR:$Rn, so_imm:$imm)]>,
+ [(ARMcmn GPR:$Rn, mod_imm:$imm)]>,
Sched<[WriteCMP, ReadALU]> {
bits<4> Rn;
bits<12> imm;
let Inst{3-0} = Rn;
}
-def MSRi : ABI<0b0011, (outs), (ins msr_mask:$mask, so_imm:$a), NoItinerary,
- "msr", "\t$mask, $a", []> {
+def MSRi : ABI<0b0011, (outs), (ins msr_mask:$mask, mod_imm:$imm), NoItinerary,
+ "msr", "\t$mask, $imm", []> {
bits<5> mask;
- bits<12> a;
+ bits<12> imm;
let Inst{23} = 0;
let Inst{22} = mask{4}; // R bit
let Inst{21-20} = 0b10;
let Inst{19-16} = mask{3-0};
let Inst{15-12} = 0b1111;
- let Inst{11-0} = a;
+ let Inst{11-0} = imm;
}
// However, the MSR (banked register) system instruction (ARMv7VE) *does* have a
// "mov Rd, so_imm_not" can be handled via "mvn" in assembly, just like
// for isel.
def : ARMInstAlias<"mov${s}${p} $Rd, $imm",
- (MVNi rGPR:$Rd, so_imm_not:$imm, pred:$p, cc_out:$s)>;
+ (MVNi rGPR:$Rd, mod_imm_not:$imm, pred:$p, cc_out:$s)>;
def : ARMInstAlias<"mvn${s}${p} $Rd, $imm",
- (MOVi rGPR:$Rd, so_imm_not:$imm, pred:$p, cc_out:$s)>;
+ (MOVi rGPR:$Rd, mod_imm_not:$imm, pred:$p, cc_out:$s)>;
// Same for AND <--> BIC
def : ARMInstAlias<"bic${s}${p} $Rd, $Rn, $imm",
- (ANDri rGPR:$Rd, rGPR:$Rn, so_imm_not:$imm,
+ (ANDri rGPR:$Rd, rGPR:$Rn, mod_imm_not:$imm,
pred:$p, cc_out:$s)>;
def : ARMInstAlias<"bic${s}${p} $Rdn, $imm",
- (ANDri rGPR:$Rdn, rGPR:$Rdn, so_imm_not:$imm,
+ (ANDri rGPR:$Rdn, rGPR:$Rdn, mod_imm_not:$imm,
pred:$p, cc_out:$s)>;
def : ARMInstAlias<"and${s}${p} $Rd, $Rn, $imm",
- (BICri rGPR:$Rd, rGPR:$Rn, so_imm_not:$imm,
+ (BICri rGPR:$Rd, rGPR:$Rn, mod_imm_not:$imm,
pred:$p, cc_out:$s)>;
def : ARMInstAlias<"and${s}${p} $Rdn, $imm",
- (BICri rGPR:$Rdn, rGPR:$Rdn, so_imm_not:$imm,
+ (BICri rGPR:$Rdn, rGPR:$Rdn, mod_imm_not:$imm,
pred:$p, cc_out:$s)>;
// Likewise, "add Rd, so_imm_neg" -> sub
def : ARMInstAlias<"add${s}${p} $Rd, $Rn, $imm",
- (SUBri GPR:$Rd, GPR:$Rn, so_imm_neg:$imm, pred:$p, cc_out:$s)>;
+ (SUBri GPR:$Rd, GPR:$Rn, mod_imm_neg:$imm, pred:$p, cc_out:$s)>;
def : ARMInstAlias<"add${s}${p} $Rd, $imm",
- (SUBri GPR:$Rd, GPR:$Rd, so_imm_neg:$imm, pred:$p, cc_out:$s)>;
+ (SUBri GPR:$Rd, GPR:$Rd, mod_imm_neg:$imm, pred:$p, cc_out:$s)>;
// Same for CMP <--> CMN via so_imm_neg
def : ARMInstAlias<"cmp${p} $Rd, $imm",
- (CMNri rGPR:$Rd, so_imm_neg:$imm, pred:$p)>;
+ (CMNri rGPR:$Rd, mod_imm_neg:$imm, pred:$p)>;
def : ARMInstAlias<"cmn${p} $Rd, $imm",
- (CMPri rGPR:$Rd, so_imm_neg:$imm, pred:$p)>;
+ (CMPri rGPR:$Rd, mod_imm_neg:$imm, pred:$p)>;
// The shifter forms of the MOV instruction are aliased to the ASR, LSL,
// LSR, ROR, and RRX instructions.
ARMAsmPrinter &AP) {
OutMI.setOpcode(MI->getOpcode());
+ // In the MC layer, we keep modified immediates in their encoded form
+ bool EncodeImms = false;
+ switch (MI->getOpcode()) {
+ default: break;
+ case ARM::MOVi:
+ case ARM::MVNi:
+ case ARM::CMPri:
+ case ARM::CMNri:
+ case ARM::TSTri:
+ case ARM::TEQri:
+ case ARM::MSRi:
+ case ARM::ADCri:
+ case ARM::ADDri:
+ case ARM::ADDSri:
+ case ARM::SBCri:
+ case ARM::SUBri:
+ case ARM::SUBSri:
+ case ARM::ANDri:
+ case ARM::ORRri:
+ case ARM::EORri:
+ case ARM::BICri:
+ case ARM::RSBri:
+ case ARM::RSBSri:
+ case ARM::RSCri:
+ EncodeImms = true;
+ break;
+ }
+
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
const MachineOperand &MO = MI->getOperand(i);
MCOperand MCOp;
- if (AP.lowerOperand(MO, MCOp))
+ if (AP.lowerOperand(MO, MCOp)) {
+ if (MCOp.isImm() && EncodeImms) {
+ int32_t Enc = ARM_AM::getSOImmVal(MCOp.getImm());
+ if (Enc != -1)
+ MCOp.setImm(Enc);
+ }
OutMI.addOperand(MCOp);
+ }
}
}
OperandMatchResultTy parseSetEndImm(OperandVector &);
OperandMatchResultTy parseShifterImm(OperandVector &);
OperandMatchResultTy parseRotImm(OperandVector &);
+ OperandMatchResultTy parseModImm(OperandVector &);
OperandMatchResultTy parseBitfield(OperandVector &);
OperandMatchResultTy parsePostIdxReg(OperandVector &);
OperandMatchResultTy parseAM3Offset(OperandVector &);
k_ShiftedImmediate,
k_ShifterImmediate,
k_RotateImmediate,
+ k_ModifiedImmediate,
k_BitfieldDescriptor,
k_Token
} Kind;
unsigned Imm;
};
+ struct ModImmOp {
+ unsigned Bits;
+ unsigned Rot;
+ };
+
struct BitfieldOp {
unsigned LSB;
unsigned Width;
struct RegShiftedRegOp RegShiftedReg;
struct RegShiftedImmOp RegShiftedImm;
struct RotImmOp RotImm;
+ struct ModImmOp ModImm;
struct BitfieldOp Bitfield;
};
case k_RotateImmediate:
RotImm = o.RotImm;
break;
+ case k_ModifiedImmediate:
+ ModImm = o.ModImm;
+ break;
case k_BitfieldDescriptor:
Bitfield = o.Bitfield;
break;
bool isRegShiftedReg() const { return Kind == k_ShiftedRegister; }
bool isRegShiftedImm() const { return Kind == k_ShiftedImmediate; }
bool isRotImm() const { return Kind == k_RotateImmediate; }
+ bool isModImm() const { return Kind == k_ModifiedImmediate; }
+ bool isModImmNot() const {
+ if (!isImm()) return false;
+ const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
+ if (!CE) return false;
+ int64_t Value = CE->getValue();
+ return ARM_AM::getSOImmVal(~Value) != -1;
+ }
+ bool isModImmNeg() const {
+ if (!isImm()) return false;
+ const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
+ if (!CE) return false;
+ int64_t Value = CE->getValue();
+ return ARM_AM::getSOImmVal(Value) == -1 &&
+ ARM_AM::getSOImmVal(-Value) != -1;
+ }
bool isBitfield() const { return Kind == k_BitfieldDescriptor; }
bool isPostIdxRegShifted() const { return Kind == k_PostIndexRegister; }
bool isPostIdxReg() const {
Inst.addOperand(MCOperand::CreateImm(RotImm.Imm >> 3));
}
+ void addModImmOperands(MCInst &Inst, unsigned N) const {
+ assert(N == 1 && "Invalid number of operands!");
+
+ // Support for fixups (MCFixup)
+ if (isImm())
+ return addImmOperands(Inst, N);
+
+ if (Inst.getOpcode() == ARM::ADDri &&
+ Inst.getOperand(1).getReg() == ARM::PC) {
+ // Instructions of the form [ADD <rd>, pc, #imm] are manually aliased
+ // in processInstruction() to use ADR. We must keep the immediate in
+ // its unencoded form in order to not clash with this aliasing.
+ Inst.addOperand(MCOperand::CreateImm(ARM_AM::rotr32(ModImm.Bits,
+ ModImm.Rot)));
+ } else {
+ Inst.addOperand(MCOperand::CreateImm(ModImm.Bits | (ModImm.Rot << 7)));
+ }
+ }
+
+ void addModImmNotOperands(MCInst &Inst, unsigned N) const {
+ assert(N == 1 && "Invalid number of operands!");
+ const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
+ uint32_t Enc = ARM_AM::getSOImmVal(~CE->getValue());
+ Inst.addOperand(MCOperand::CreateImm(Enc));
+ }
+
+ void addModImmNegOperands(MCInst &Inst, unsigned N) const {
+ assert(N == 1 && "Invalid number of operands!");
+ const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
+ uint32_t Enc = ARM_AM::getSOImmVal(-CE->getValue());
+ Inst.addOperand(MCOperand::CreateImm(Enc));
+ }
+
void addBitfieldOperands(MCInst &Inst, unsigned N) const {
assert(N == 1 && "Invalid number of operands!");
// Munge the lsb/width into a bitfield mask.
return Op;
}
+ static std::unique_ptr<ARMOperand> CreateModImm(unsigned Bits, unsigned Rot,
+ SMLoc S, SMLoc E) {
+ auto Op = make_unique<ARMOperand>(k_ModifiedImmediate);
+ Op->ModImm.Bits = Bits;
+ Op->ModImm.Rot = Rot;
+ Op->StartLoc = S;
+ Op->EndLoc = E;
+ return Op;
+ }
+
static std::unique_ptr<ARMOperand>
CreateBitfield(unsigned LSB, unsigned Width, SMLoc S, SMLoc E) {
auto Op = make_unique<ARMOperand>(k_BitfieldDescriptor);
case k_RotateImmediate:
OS << "<ror " << " #" << (RotImm.Imm * 8) << ">";
break;
+ case k_ModifiedImmediate:
+ OS << "<mod_imm #" << ModImm.Bits << ", #"
+ << ModImm.Rot << ")>";
+ break;
case k_BitfieldDescriptor:
OS << "<bitfield " << "lsb: " << Bitfield.LSB
<< ", width: " << Bitfield.Width << ">";
}
ARMAsmParser::OperandMatchResultTy
+ARMAsmParser::parseModImm(OperandVector &Operands) {
+ MCAsmParser &Parser = getParser();
+ MCAsmLexer &Lexer = getLexer();
+ int64_t Imm1, Imm2;
+
+ if ((Parser.getTok().isNot(AsmToken::Hash) &&
+ Parser.getTok().isNot(AsmToken::Dollar) /* looking for an immediate */ )
+ || Lexer.peekTok().is(AsmToken::Colon)
+ || Lexer.peekTok().is(AsmToken::LParen) /* avoid complex operands */ )
+ return MatchOperand_NoMatch;
+
+ SMLoc S = Parser.getTok().getLoc();
+
+ // Eat the hash (or dollar)
+ Parser.Lex();
+
+ SMLoc Sx1, Ex1;
+ Sx1 = Parser.getTok().getLoc();
+ const MCExpr *Imm1Exp;
+ if (getParser().parseExpression(Imm1Exp, Ex1)) {
+ Error(Sx1, "malformed expression");
+ return MatchOperand_ParseFail;
+ }
+
+ const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Imm1Exp);
+
+ if (CE) {
+ // immediate must fit within 32-bits
+ Imm1 = CE->getValue();
+ if (Imm1 < INT32_MIN || Imm1 > UINT32_MAX) {
+ Error(Sx1, "immediate operand must be representable with 32 bits");
+ return MatchOperand_ParseFail;
+ }
+
+ int Enc = ARM_AM::getSOImmVal(Imm1);
+ if (Enc != -1 && Parser.getTok().is(AsmToken::EndOfStatement)) {
+ // We have a match!
+ Operands.push_back(ARMOperand::CreateModImm((Enc & 0xFF),
+ (Enc & 0xF00) >> 7,
+ Sx1, Ex1));
+ return MatchOperand_Success;
+ }
+ } else {
+ Error(Sx1, "constant expression expected");
+ return MatchOperand_ParseFail;
+ }
+
+ if (Parser.getTok().isNot(AsmToken::Comma)) {
+ // Consider [mov r0, #-10], which is aliased with mvn. We cannot fail
+ // the parse here.
+ Operands.push_back(ARMOperand::CreateImm(Imm1Exp, Sx1, Ex1));
+ return MatchOperand_Success;
+ }
+
+ // From this point onward, we expect the input to be a (#bits, #rot) pair
+ if (Imm1 & ~0xFF) {
+ Error(Sx1, "immediate operand must a number in the range [0, 255]");
+ return MatchOperand_ParseFail;
+ }
+
+ if (Lexer.peekTok().isNot(AsmToken::Hash) &&
+ Lexer.peekTok().isNot(AsmToken::Dollar)) {
+ Error(Lexer.peekTok().getLoc(), "immediate operand expected");
+ return MatchOperand_ParseFail;
+ }
+
+ // Eat the comma
+ Parser.Lex();
+
+ // Repeat for #rot
+ SMLoc Sx2, Ex2;
+ Sx2 = Parser.getTok().getLoc();
+
+ // Eat the hash (or dollar)
+ Parser.Lex();
+
+ const MCExpr *Imm2Exp;
+ if (getParser().parseExpression(Imm2Exp, Ex2)) {
+ Error(Sx2, "malformed expression");
+ return MatchOperand_ParseFail;
+ }
+
+ CE = dyn_cast<MCConstantExpr>(Imm2Exp);
+
+ if (CE) {
+ Imm2 = CE->getValue();
+ if (!(Imm2 & ~0x1E)) {
+ // We have a match!
+ Operands.push_back(ARMOperand::CreateModImm(Imm1, Imm2, S, Ex2));
+ return MatchOperand_Success;
+ }
+ Error(Sx2, "immediate operand must an even number in the range [0, 30]");
+ return MatchOperand_ParseFail;
+ } else {
+ Error(Sx2, "constant expression expected");
+ return MatchOperand_ParseFail;
+ }
+}
+
+ARMAsmParser::OperandMatchResultTy
ARMAsmParser::parseBitfield(OperandVector &Operands) {
MCAsmParser &Parser = getParser();
SMLoc S = Parser.getTok().getLoc();
if (CE->getValue() == 0)
return Match_Success;
break;
+ case MCK_ModImm:
case MCK_ARMSOImm:
if (Op.isImm()) {
const MCExpr *SOExpr = Op.getImm();
O << markup(">");
}
+void ARMInstPrinter::printModImmOperand(const MCInst *MI, unsigned OpNum,
+ raw_ostream &O) {
+ MCOperand Op = MI->getOperand(OpNum);
+
+ // Support for fixups (MCFixup)
+ if (Op.isExpr())
+ return printOperand(MI, OpNum, O);
+
+ unsigned Bits = Op.getImm() & 0xFF;
+ unsigned Rot = (Op.getImm() & 0xF00) >> 7;
+
+ bool PrintUnsigned = false;
+ switch (MI->getOpcode()){
+ case ARM::MOVi:
+ // Movs to PC should be treated unsigned
+ PrintUnsigned = (MI->getOperand(OpNum - 1).getReg() == ARM::PC);
+ break;
+ case ARM::MSRi:
+ // Movs to special registers should be treated unsigned
+ PrintUnsigned = true;
+ break;
+ }
+
+ int32_t Rotated = ARM_AM::rotr32(Bits, Rot);
+ if (ARM_AM::getSOImmVal(Rotated) == Op.getImm()) {
+ // #rot has the least possible value
+ O << "#" << markup("<imm:");
+ if (PrintUnsigned)
+ O << static_cast<uint32_t>(Rotated);
+ else
+ O << Rotated;
+ O << markup(">");
+ return;
+ }
+
+ // Explicit #bits, #rot implied
+ O << "#"
+ << markup("<imm:")
+ << Bits
+ << markup(">")
+ << ", #"
+ << markup("<imm:")
+ << Rot
+ << markup(">");
+}
+
void ARMInstPrinter::printFBits16(const MCInst *MI, unsigned OpNum,
raw_ostream &O) {
O << markup("<imm:")
void printNEONModImmOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O);
void printImmPlusOneOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O);
void printRotImmOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O);
+ void printModImmOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O);
void printGPRPairOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O);
void printPCLabel(const MCInst *MI, unsigned OpNum, raw_ostream &O);
return Binary;
}
+ unsigned getModImmOpValue(const MCInst &MI, unsigned Op,
+ SmallVectorImpl<MCFixup> &Fixups,
+ const MCSubtargetInfo &ST) const {
+ const MCOperand &MO = MI.getOperand(Op);
+
+ // Support for fixups (MCFixup)
+ if (MO.isExpr()) {
+ const MCExpr *Expr = MO.getExpr();
+ // In instruction code this value always encoded as lowest 12 bits,
+ // so we don't have to perform any specific adjustments.
+ // Due to requirements of relocatable records we have to use FK_Data_4.
+ // See ARMELFObjectWriter::ExplicitRelSym and
+ // ARMELFObjectWriter::GetRelocTypeInner for more details.
+ MCFixupKind Kind = MCFixupKind(FK_Data_4);
+ Fixups.push_back(MCFixup::Create(0, Expr, Kind, MI.getLoc()));
+ return 0;
+ }
+
+ // Immediate is already in its encoded format
+ return MO.getImm();
+ }
+
/// getT2SOImmOpValue - Return an encoded 12-bit shifted-immediate value.
unsigned getT2SOImmOpValue(const MCInst &MI, unsigned Op,
SmallVectorImpl<MCFixup> &Fixups,
@ ADC (immediate)
@------------------------------------------------------------------------------
adc r1, r2, #0xf
+ adc r7, r8, #42, #2
+ adc r7, r8, #-2147483638
+ adc r7, r8, #40, #2
adc r1, r2, #0xf0
adc r1, r2, #0xf00
adc r1, r2, #0xf000
adc r1, r2, #0xf0000000
adc r1, r2, #0xf000000f
adcs r1, r2, #0xf00
+ adcs r7, r8, #40, #2
adcseq r1, r2, #0xf00
adceq r1, r2, #0xf00
@ CHECK: adc r1, r2, #15 @ encoding: [0x0f,0x10,0xa2,0xe2]
+@ CHECK: adc r7, r8, #-2147483638 @ encoding: [0x2a,0x71,0xa8,0xe2]
+@ CHECK: adc r7, r8, #-2147483638 @ encoding: [0x2a,0x71,0xa8,0xe2]
+@ CHECK: adc r7, r8, #40, #2 @ encoding: [0x28,0x71,0xa8,0xe2]
@ CHECK: adc r1, r2, #240 @ encoding: [0xf0,0x10,0xa2,0xe2]
@ CHECK: adc r1, r2, #3840 @ encoding: [0x0f,0x1c,0xa2,0xe2]
@ CHECK: adc r1, r2, #61440 @ encoding: [0x0f,0x1a,0xa2,0xe2]
@ CHECK: adc r1, r2, #983040 @ encoding: [0x0f,0x18,0xa2,0xe2]
@ CHECK: adc r1, r2, #15728640 @ encoding: [0x0f,0x16,0xa2,0xe2]
@ CHECK: adc r1, r2, #251658240 @ encoding: [0x0f,0x14,0xa2,0xe2]
-@ CHECK: adc r1, r2, #4026531840 @ encoding: [0x0f,0x12,0xa2,0xe2]
-@ CHECK: adc r1, r2, #4026531855 @ encoding: [0xff,0x12,0xa2,0xe2]
-
+@ CHECK: adc r1, r2, #-268435456 @ encoding: [0x0f,0x12,0xa2,0xe2]
+@ CHECK: adc r1, r2, #-268435441 @ encoding: [0xff,0x12,0xa2,0xe2]
@ CHECK: adcs r1, r2, #3840 @ encoding: [0x0f,0x1c,0xb2,0xe2]
+@ CHECK: adcs r7, r8, #40, #2 @ encoding: [0x28,0x71,0xb8,0xe2]
@ CHECK: adcseq r1, r2, #3840 @ encoding: [0x0f,0x1c,0xb2,0x02]
@ CHECK: adceq r1, r2, #3840 @ encoding: [0x0f,0x1c,0xa2,0x02]
@ ADD
@------------------------------------------------------------------------------
add r4, r5, #0xf000
+ add r7, r8, #42, #2
+ add r7, r8, #-2147483638
+ add r7, r8, #40, #2
add r4, r5, r6
add r4, r5, r6, lsl #5
add r4, r5, r6, lsr #5
add r0, pc, #(Lback - .)
@ CHECK: add r4, r5, #61440 @ encoding: [0x0f,0x4a,0x85,0xe2]
+@ CHECK: add r7, r8, #-2147483638 @ encoding: [0x2a,0x71,0x88,0xe2]
+@ CHECK: add r7, r8, #-2147483638 @ encoding: [0x2a,0x71,0x88,0xe2]
+@ CHECK: add r7, r8, #40, #2 @ encoding: [0x28,0x71,0x88,0xe2]
@ CHECK: add r4, r5, r6 @ encoding: [0x06,0x40,0x85,0xe0]
@ CHECK: add r4, r5, r6, lsl #5 @ encoding: [0x86,0x42,0x85,0xe0]
@ CHECK: add r4, r5, r6, lsr #5 @ encoding: [0xa6,0x42,0x85,0xe0]
@ CHECK: add r3, r1, r2, asr #32 @ encoding: [0x42,0x30,0x81,0xe0]
@------------------------------------------------------------------------------
+@ ADDS
+@------------------------------------------------------------------------------
+ adds r7, r8, #42, #2
+ adds r7, r8, #-2147483638
+ adds r7, r8, #40, #2
+
+@ CHECK: adds r7, r8, #-2147483638 @ encoding: [0x2a,0x71,0x98,0xe2]
+@ CHECK: adds r7, r8, #-2147483638 @ encoding: [0x2a,0x71,0x98,0xe2]
+@ CHECK: adds r7, r8, #40, #2 @ encoding: [0x28,0x71,0x98,0xe2]
+
+@------------------------------------------------------------------------------
@ AND
@------------------------------------------------------------------------------
and r10, r1, #0xf
+ and r7, r8, #42, #2
+ and r7, r8, #-2147483638
+ and r7, r8, #40, #2
and r10, r1, r6
and r10, r1, r6, lsl #10
and r10, r1, r6, lsr #10
and r10, r1, rrx
@ CHECK: and r10, r1, #15 @ encoding: [0x0f,0xa0,0x01,0xe2]
+@ CHECK: and r7, r8, #-2147483638 @ encoding: [0x2a,0x71,0x08,0xe2]
+@ CHECK: and r7, r8, #-2147483638 @ encoding: [0x2a,0x71,0x08,0xe2]
+@ CHECK: and r7, r8, #40, #2 @ encoding: [0x28,0x71,0x08,0xe2]
@ CHECK: and r10, r1, r6 @ encoding: [0x06,0xa0,0x01,0xe0]
@ CHECK: and r10, r1, r6, lsl #10 @ encoding: [0x06,0xa5,0x01,0xe0]
@ CHECK: and r10, r1, r6, lsr #10 @ encoding: [0x26,0xa5,0x01,0xe0]
@ BIC
@------------------------------------------------------------------------------
bic r10, r1, #0xf
+ bic r7, r8, #42, #2
+ bic r7, r8, #-2147483638
+ bic r7, r8, #40, #2
bic r10, r1, r6
bic r10, r1, r6, lsl #10
bic r10, r1, r6, lsr #10
@ destination register is optional
bic r1, #0xf
+ bic r7, #42, #2
+ bic r7, #-2147483638
+ bic r7, #40, #2
bic r10, r1
bic r10, r1, lsl #10
bic r10, r1, lsr #10
bic r10, r1, rrx
@ CHECK: bic r10, r1, #15 @ encoding: [0x0f,0xa0,0xc1,0xe3]
+@ CHECK: bic r7, r8, #-2147483638 @ encoding: [0x2a,0x71,0xc8,0xe3]
+@ CHECK: bic r7, r8, #-2147483638 @ encoding: [0x2a,0x71,0xc8,0xe3]
+@ CHECK: bic r7, r8, #40, #2 @ encoding: [0x28,0x71,0xc8,0xe3]
@ CHECK: bic r10, r1, r6 @ encoding: [0x06,0xa0,0xc1,0xe1]
@ CHECK: bic r10, r1, r6, lsl #10 @ encoding: [0x06,0xa5,0xc1,0xe1]
@ CHECK: bic r10, r1, r6, lsr #10 @ encoding: [0x26,0xa5,0xc1,0xe1]
@ CHECK: bic r1, r1, #15 @ encoding: [0x0f,0x10,0xc1,0xe3]
+@ CHECK: bic r7, r7, #-2147483638 @ encoding: [0x2a,0x71,0xc7,0xe3]
+@ CHECK: bic r7, r7, #-2147483638 @ encoding: [0x2a,0x71,0xc7,0xe3]
+@ CHECK: bic r7, r7, #40, #2 @ encoding: [0x28,0x71,0xc7,0xe3]
@ CHECK: bic r10, r10, r1 @ encoding: [0x01,0xa0,0xca,0xe1]
@ CHECK: bic r10, r10, r1, lsl #10 @ encoding: [0x01,0xa5,0xca,0xe1]
@ CHECK: bic r10, r10, r1, lsr #10 @ encoding: [0x21,0xa5,0xca,0xe1]
@ CMN
@------------------------------------------------------------------------------
cmn r1, #0xf
+ cmn r7, #42, #2
+ cmn r7, #-2147483638
+ cmn r7, #40, #2
cmn r1, r6
cmn r1, r6, lsl #10
cmn r1, r6, lsr #10
cmn r1, r6, rrx
@ CHECK: cmn r1, #15 @ encoding: [0x0f,0x00,0x71,0xe3]
+@ CHECK: cmn r7, #-2147483638 @ encoding: [0x2a,0x01,0x77,0xe3]
+@ CHECK: cmn r7, #-2147483638 @ encoding: [0x2a,0x01,0x77,0xe3]
+@ CHECK: cmn r7, #40, #2 @ encoding: [0x28,0x01,0x77,0xe3]
@ CHECK: cmn r1, r6 @ encoding: [0x06,0x00,0x71,0xe1]
@ CHECK: cmn r1, r6, lsl #10 @ encoding: [0x06,0x05,0x71,0xe1]
@ CHECK: cmn r1, r6, lsr #10 @ encoding: [0x26,0x05,0x71,0xe1]
@ CMP
@------------------------------------------------------------------------------
cmp r1, #0xf
+ cmp r7, #42, #2
+ cmp r7, #-2147483638
+ cmp r7, #40, #2
cmp r1, r6
cmp r1, r6, lsl #10
cmp r1, r6, lsr #10
cmp lr, #0
@ CHECK: cmp r1, #15 @ encoding: [0x0f,0x00,0x51,0xe3]
+@ CHECK: cmp r7, #-2147483638 @ encoding: [0x2a,0x01,0x57,0xe3]
+@ CHECK: cmp r7, #-2147483638 @ encoding: [0x2a,0x01,0x57,0xe3]
+@ CHECK: cmp r7, #40, #2 @ encoding: [0x28,0x01,0x57,0xe3]
@ CHECK: cmp r1, r6 @ encoding: [0x06,0x00,0x51,0xe1]
@ CHECK: cmp r1, r6, lsl #10 @ encoding: [0x06,0x05,0x51,0xe1]
@ CHECK: cmp r1, r6, lsr #10 @ encoding: [0x26,0x05,0x51,0xe1]
@ EOR
@------------------------------------------------------------------------------
eor r4, r5, #0xf000
+ eor r7, r8, #42, #2
+ eor r7, r8, #-2147483638
+ eor r7, r8, #40, #2
eor r4, r5, r6
eor r4, r5, r6, lsl #5
eor r4, r5, r6, lsr #5
eor r4, r5, rrx
@ CHECK: eor r4, r5, #61440 @ encoding: [0x0f,0x4a,0x25,0xe2]
+@ CHECK: eor r7, r8, #-2147483638 @ encoding: [0x2a,0x71,0x28,0xe2]
+@ CHECK: eor r7, r8, #-2147483638 @ encoding: [0x2a,0x71,0x28,0xe2]
+@ CHECK: eor r7, r8, #40, #2 @ encoding: [0x28,0x71,0x28,0xe2]
@ CHECK: eor r4, r5, r6 @ encoding: [0x06,0x40,0x25,0xe0]
@ CHECK: eor r4, r5, r6, lsl #5 @ encoding: [0x86,0x42,0x25,0xe0]
@ CHECK: eor r4, r5, r6, lsr #5 @ encoding: [0xa6,0x42,0x25,0xe0]
mov r3, #7
mov r4, #0xff0
mov r5, #0xff0000
+ mov r7, #0, #2
+ mov r7, #42, #0
+ mov r7, #40, #2
+ mov r7, #42, #10
+ mov r7, #42, #30
+ mov r7, #42, #2
+ mov r7, #-2147483638
+ mov pc, #42, #2
mov r6, #0xffff
movw r9, #0xffff
movs r3, #7
@ CHECK: mov r3, #7 @ encoding: [0x07,0x30,0xa0,0xe3]
@ CHECK: mov r4, #4080 @ encoding: [0xff,0x4e,0xa0,0xe3]
@ CHECK: mov r5, #16711680 @ encoding: [0xff,0x58,0xa0,0xe3]
+@ CHECK: mov r7, #0, #2 @ encoding: [0x00,0x71,0xa0,0xe3]
+@ CHECK: mov r7, #42 @ encoding: [0x2a,0x70,0xa0,0xe3]
+@ CHECK: mov r7, #40, #2 @ encoding: [0x28,0x71,0xa0,0xe3]
+@ CHECK: mov r7, #176160768 @ encoding: [0x2a,0x75,0xa0,0xe3]
+@ CHECK: mov r7, #42, #30 @ encoding: [0x2a,0x7f,0xa0,0xe3]
+@ CHECK: mov r7, #-2147483638 @ encoding: [0x2a,0x71,0xa0,0xe3]
+@ CHECK: mov r7, #-2147483638 @ encoding: [0x2a,0x71,0xa0,0xe3]
+@ CHECK: mov pc, #2147483658 @ encoding: [0x2a,0xf1,0xa0,0xe3]
@ CHECK: movw r6, #65535 @ encoding: [0xff,0x6f,0x0f,0xe3]
@ CHECK: movw r9, #65535 @ encoding: [0xff,0x9f,0x0f,0xe3]
@ CHECK: movs r3, #7 @ encoding: [0x07,0x30,0xb0,0xe3]
msr spsr_fc, #5
msr SPSR_fsxc, #5
msr cpsr_fsxc, #5
+ msr APSR_nzcvq, #42, #2
+ msr apsr_nzcvqg, #2147483658
+ msr SPSR_fsxc, #40, #2
@ CHECK: msr APSR_nzcvq, #5 @ encoding: [0x05,0xf0,0x28,0xe3]
@ CHECK: msr APSR_g, #5 @ encoding: [0x05,0xf0,0x24,0xe3]
@ CHECK: msr SPSR_fc, #5 @ encoding: [0x05,0xf0,0x69,0xe3]
@ CHECK: msr SPSR_fsxc, #5 @ encoding: [0x05,0xf0,0x6f,0xe3]
@ CHECK: msr CPSR_fsxc, #5 @ encoding: [0x05,0xf0,0x2f,0xe3]
+@ CHECK: msr APSR_nzcvq, #2147483658 @ encoding: [0x2a,0xf1,0x28,0xe3]
+@ CHECK: msr APSR_nzcvqg, #2147483658 @ encoding: [0x2a,0xf1,0x2c,0xe3]
+@ CHECK: msr SPSR_fsxc, #40, #2 @ encoding: [0x28,0xf1,0x6f,0xe3]
msr apsr, r0
msr apsr_g, r0
mvn r3, #7
mvn r4, #0xff0
mvn r5, #0xff0000
+ mvn r7, #42, #2
+ mvn r7, #-2147483638
+ mvn r7, #40, #2
mvns r3, #7
mvneq r4, #0xff0
mvnseq r5, #0xff0000
@ CHECK: mvn r3, #7 @ encoding: [0x07,0x30,0xe0,0xe3]
@ CHECK: mvn r4, #4080 @ encoding: [0xff,0x4e,0xe0,0xe3]
@ CHECK: mvn r5, #16711680 @ encoding: [0xff,0x58,0xe0,0xe3]
+@ CHECK: mvn r7, #-2147483638 @ encoding: [0x2a,0x71,0xe0,0xe3]
+@ CHECK: mvn r7, #-2147483638 @ encoding: [0x2a,0x71,0xe0,0xe3]
+@ CHECK: mvn r7, #40, #2 @ encoding: [0x28,0x71,0xe0,0xe3]
@ CHECK: mvns r3, #7 @ encoding: [0x07,0x30,0xf0,0xe3]
@ CHECK: mvneq r4, #4080 @ encoding: [0xff,0x4e,0xe0,0x03]
@ CHECK: mvnseq r5, #16711680 @ encoding: [0xff,0x58,0xf0,0x03]
@ ORR
@------------------------------------------------------------------------------
orr r4, r5, #0xf000
+ orr r7, r8, #42, #2
+ orr r7, r8, #-2147483638
+ orr r7, r8, #40, #2
orr r4, r5, r6
orr r4, r5, r6, lsl #5
orr r4, r5, r6, lsr #5
orr r4, r5, rrx
@ CHECK: orr r4, r5, #61440 @ encoding: [0x0f,0x4a,0x85,0xe3]
+@ CHECK: orr r7, r8, #-2147483638 @ encoding: [0x2a,0x71,0x88,0xe3]
+@ CHECK: orr r7, r8, #-2147483638 @ encoding: [0x2a,0x71,0x88,0xe3]
+@ CHECK: orr r7, r8, #40, #2 @ encoding: [0x28,0x71,0x88,0xe3]
@ CHECK: orr r4, r5, r6 @ encoding: [0x06,0x40,0x85,0xe1]
@ CHECK: orr r4, r5, r6, lsl #5 @ encoding: [0x86,0x42,0x85,0xe1]
@ CHECK: orr r4, r5, r6, lsr #5 @ encoding: [0xa6,0x42,0x85,0xe1]
@ RSB
@------------------------------------------------------------------------------
rsb r4, r5, #0xf000
+ rsb r7, r8, #42, #2
+ rsb r7, r8, #-2147483638
+ rsb r7, r8, #40, #2
rsb r4, r5, r6
rsb r4, r5, r6, lsl #5
rsblo r4, r5, r6, lsr #5
rsb r4, r5, rrx
@ CHECK: rsb r4, r5, #61440 @ encoding: [0x0f,0x4a,0x65,0xe2]
+@ CHECK: rsb r7, r8, #-2147483638 @ encoding: [0x2a,0x71,0x68,0xe2]
+@ CHECK: rsb r7, r8, #-2147483638 @ encoding: [0x2a,0x71,0x68,0xe2]
+@ CHECK: rsb r7, r8, #40, #2 @ encoding: [0x28,0x71,0x68,0xe2]
@ CHECK: rsb r4, r5, r6 @ encoding: [0x06,0x40,0x65,0xe0]
@ CHECK: rsb r4, r5, r6, lsl #5 @ encoding: [0x86,0x42,0x65,0xe0]
@ CHECK: rsblo r4, r5, r6, lsr #5 @ encoding: [0xa6,0x42,0x65,0x30]
@ CHECK: rsb r4, r4, r5, rrx @ encoding: [0x65,0x40,0x64,0xe0]
@------------------------------------------------------------------------------
+@ RSBS
+@------------------------------------------------------------------------------
+ rsbs r7, r8, #42, #2
+ rsbs r7, r8, #-2147483638
+ rsbs r7, r8, #40, #2
+
+@ CHECK: rsbs r7, r8, #-2147483638 @ encoding: [0x2a,0x71,0x78,0xe2]
+@ CHECK: rsbs r7, r8, #-2147483638 @ encoding: [0x2a,0x71,0x78,0xe2]
+@ CHECK: rsbs r7, r8, #40, #2 @ encoding: [0x28,0x71,0x78,0xe2]
+
+@------------------------------------------------------------------------------
@ RSC
@------------------------------------------------------------------------------
rsc r4, r5, #0xf000
+ rsc r7, r8, #42, #2
+ rsc r7, r8, #-2147483638
+ rsc r7, r8, #40, #2
rsc r4, r5, r6
rsc r4, r5, r6, lsl #5
rsclo r4, r5, r6, lsr #5
rsc r6, r7, ror r9
@ CHECK: rsc r4, r5, #61440 @ encoding: [0x0f,0x4a,0xe5,0xe2]
+@ CHECK: rsc r7, r8, #-2147483638 @ encoding: [0x2a,0x71,0xe8,0xe2]
+@ CHECK: rsc r7, r8, #-2147483638 @ encoding: [0x2a,0x71,0xe8,0xe2]
+@ CHECK: rsc r7, r8, #40, #2 @ encoding: [0x28,0x71,0xe8,0xe2]
@ CHECK: rsc r4, r5, r6 @ encoding: [0x06,0x40,0xe5,0xe0]
@ CHECK: rsc r4, r5, r6, lsl #5 @ encoding: [0x86,0x42,0xe5,0xe0]
@ CHECK: rsclo r4, r5, r6, lsr #5 @ encoding: [0xa6,0x42,0xe5,0x30]
@ SBC
@------------------------------------------------------------------------------
sbc r4, r5, #0xf000
+ sbc r7, r8, #42, #2
+ sbc r7, r8, #-2147483638
+ sbc r7, r8, #40, #2
sbc r4, r5, r6
sbc r4, r5, r6, lsl #5
sbc r4, r5, r6, lsr #5
sbc r6, r7, ror r9
@ CHECK: sbc r4, r5, #61440 @ encoding: [0x0f,0x4a,0xc5,0xe2]
+@ CHECK: sbc r7, r8, #-2147483638 @ encoding: [0x2a,0x71,0xc8,0xe2]
+@ CHECK: sbc r7, r8, #-2147483638 @ encoding: [0x2a,0x71,0xc8,0xe2]
+@ CHECK: sbc r7, r8, #40, #2 @ encoding: [0x28,0x71,0xc8,0xe2]
@ CHECK: sbc r4, r5, r6 @ encoding: [0x06,0x40,0xc5,0xe0]
@ CHECK: sbc r4, r5, r6, lsl #5 @ encoding: [0x86,0x42,0xc5,0xe0]
@ CHECK: sbc r4, r5, r6, lsr #5 @ encoding: [0xa6,0x42,0xc5,0xe0]
@ SUB
@------------------------------------------------------------------------------
sub r4, r5, #0xf000
+ sub r7, r8, #42, #2
+ sub r7, r8, #-2147483638
+ sub r7, r8, #40, #2
sub r4, r5, r6
sub r4, r5, r6, lsl #5
sub r4, r5, r6, lsr #5
sub r6, r7, ror r9
@ CHECK: sub r4, r5, #61440 @ encoding: [0x0f,0x4a,0x45,0xe2]
+@ CHECK: sub r7, r8, #-2147483638 @ encoding: [0x2a,0x71,0x48,0xe2]
+@ CHECK: sub r7, r8, #-2147483638 @ encoding: [0x2a,0x71,0x48,0xe2]
+@ CHECK: sub r7, r8, #40, #2 @ encoding: [0x28,0x71,0x48,0xe2]
@ CHECK: sub r4, r5, r6 @ encoding: [0x06,0x40,0x45,0xe0]
@ CHECK: sub r4, r5, r6, lsl #5 @ encoding: [0x86,0x42,0x45,0xe0]
@ CHECK: sub r4, r5, r6, lsr #5 @ encoding: [0xa6,0x42,0x45,0xe0]
@ CHECK: sub r3, r1, r2, asr #32 @ encoding: [0x42,0x30,0x41,0xe0]
@------------------------------------------------------------------------------
+@ SUBS
+@------------------------------------------------------------------------------
+ subs r7, r8, #42, #2
+ subs r7, r8, #-2147483638
+ subs r7, r8, #40, #2
+
+@ CHECK: subs r7, r8, #-2147483638 @ encoding: [0x2a,0x71,0x58,0xe2]
+@ CHECK: subs r7, r8, #-2147483638 @ encoding: [0x2a,0x71,0x58,0xe2]
+@ CHECK: subs r7, r8, #40, #2 @ encoding: [0x28,0x71,0x58,0xe2]
+
+@------------------------------------------------------------------------------
@ SVC
@------------------------------------------------------------------------------
svc #16
@ TEQ
@------------------------------------------------------------------------------
teq r5, #0xf000
+ teq r7, #42, #2
+ teq r7, #-2147483638
+ teq r7, #40, #2
teq r4, r5
teq r4, r5, lsl #5
teq r4, r5, lsr #5
teq r6, r7, ror r9
@ CHECK: teq r5, #61440 @ encoding: [0x0f,0x0a,0x35,0xe3]
+@ CHECK: teq r7, #-2147483638 @ encoding: [0x2a,0x01,0x37,0xe3]
+@ CHECK: teq r7, #-2147483638 @ encoding: [0x2a,0x01,0x37,0xe3]
+@ CHECK: teq r7, #40, #2 @ encoding: [0x28,0x01,0x37,0xe3]
@ CHECK: teq r4, r5 @ encoding: [0x05,0x00,0x34,0xe1]
@ CHECK: teq r4, r5, lsl #5 @ encoding: [0x85,0x02,0x34,0xe1]
@ CHECK: teq r4, r5, lsr #5 @ encoding: [0xa5,0x02,0x34,0xe1]
@ TST
@------------------------------------------------------------------------------
tst r5, #0xf000
+ tst r7, #42, #2
+ tst r7, #-2147483638
+ tst r7, #40, #2
tst r4, r5
tst r4, r5, lsl #5
tst r4, r5, lsr #5
tst r6, r7, ror r9
@ CHECK: tst r5, #61440 @ encoding: [0x0f,0x0a,0x15,0xe3]
+@ CHECK: tst r7, #-2147483638 @ encoding: [0x2a,0x01,0x17,0xe3]
+@ CHECK: tst r7, #-2147483638 @ encoding: [0x2a,0x01,0x17,0xe3]
+@ CHECK: tst r7, #40, #2 @ encoding: [0x28,0x01,0x17,0xe3]
@ CHECK: tst r4, r5 @ encoding: [0x05,0x00,0x14,0xe1]
@ CHECK: tst r4, r5, lsl #5 @ encoding: [0x85,0x02,0x14,0xe1]
@ CHECK: tst r4, r5, lsr #5 @ encoding: [0xa5,0x02,0x14,0xe1]
@ CHECK-ERRORS: error: destination register and base register can't be identical
@ CHECK-ERRORS: ldrsb r0, [r0], r1
@ CHECK-ERRORS: ^
+
+ @ Out of range modified immediate values
+ mov r5, #-256, #6
+ mov r6, #42, #7
+ mvn r5, #256, #6
+ mvn r6, #42, #298
+ cmp r5, #65535, #6
+ cmp r6, #42, #31
+ cmn r5, #-1, #6
+ cmn r6, #42, #32
+ msr APSR_nzcvq, #-128, #2
+ msr apsr_nzcvqg, #0, #1
+ adc r7, r8, #-256, #2
+ adc r7, r8, #128, #1
+ sbc r7, r8, #-256, #2
+ sbc r7, r8, #128, #1
+ add r7, r8, #-2149, #0
+ add r7, r8, #100, #1
+ sub r7, r8, #-2149, #0
+ sub r7, r8, #100, #1
+ and r7, r8, #-2149, #0
+ and r7, r8, #100, #1
+ orr r7, r8, #-2149, #0
+ orr r7, r8, #100, #1
+ eor r7, r8, #-2149, #0
+ eor r7, r8, #100, #1
+ bic r7, r8, #-2149, #0
+ bic r7, r8, #100, #1
+ rsb r7, r8, #-2149, #0
+ rsb r7, r8, #100, #1
+ adds r7, r8, #-2149, #0
+ adds r7, r8, #100, #1
+ subs r7, r8, #-2149, #0
+ subs r7, r8, #100, #1
+ rsbs r7, r8, #-2149, #0
+ rsbs r7, r8, #100, #1
+ rsc r7, r8, #-2149, #0
+ rsc r7, r8, #100, #1
+ TST r7, #-2149, #0
+ TST r7, #100, #1
+ TEQ r7, #-2149, #0
+ TEQ r7, #100, #1
+@ CHECK-ERRORS: error: immediate operand must a number in the range [0, 255]
+@ CHECK-ERRORS: error: immediate operand must an even number in the range [0, 30]
+@ CHECK-ERRORS: error: immediate operand must a number in the range [0, 255]
+@ CHECK-ERRORS: error: immediate operand must an even number in the range [0, 30]
+@ CHECK-ERRORS: error: immediate operand must a number in the range [0, 255]
+@ CHECK-ERRORS: error: immediate operand must an even number in the range [0, 30]
+@ CHECK-ERRORS: error: immediate operand must a number in the range [0, 255]
+@ CHECK-ERRORS: error: immediate operand must an even number in the range [0, 30]
+@ CHECK-ERRORS: error: immediate operand must a number in the range [0, 255]
+@ CHECK-ERRORS: error: immediate operand must an even number in the range [0, 30]
+@ CHECK-ERRORS: error: immediate operand must a number in the range [0, 255]
+@ CHECK-ERRORS: error: immediate operand must an even number in the range [0, 30]
+@ CHECK-ERRORS: error: immediate operand must a number in the range [0, 255]
+@ CHECK-ERRORS: error: immediate operand must an even number in the range [0, 30]
+@ CHECK-ERRORS: error: immediate operand must a number in the range [0, 255]
+@ CHECK-ERRORS: error: immediate operand must an even number in the range [0, 30]
+@ CHECK-ERRORS: error: immediate operand must a number in the range [0, 255]
+@ CHECK-ERRORS: error: immediate operand must an even number in the range [0, 30]
+@ CHECK-ERRORS: error: immediate operand must a number in the range [0, 255]
+@ CHECK-ERRORS: error: immediate operand must an even number in the range [0, 30]
+@ CHECK-ERRORS: error: immediate operand must a number in the range [0, 255]
+@ CHECK-ERRORS: error: immediate operand must an even number in the range [0, 30]
+@ CHECK-ERRORS: error: immediate operand must a number in the range [0, 255]
+@ CHECK-ERRORS: error: immediate operand must an even number in the range [0, 30]
+@ CHECK-ERRORS: error: immediate operand must a number in the range [0, 255]
+@ CHECK-ERRORS: error: immediate operand must an even number in the range [0, 30]
+@ CHECK-ERRORS: error: immediate operand must a number in the range [0, 255]
+@ CHECK-ERRORS: error: immediate operand must an even number in the range [0, 30]
+@ CHECK-ERRORS: error: immediate operand must a number in the range [0, 255]
+@ CHECK-ERRORS: error: immediate operand must an even number in the range [0, 30]
+@ CHECK-ERRORS: error: immediate operand must a number in the range [0, 255]
+@ CHECK-ERRORS: error: immediate operand must an even number in the range [0, 30]
+@ CHECK-ERRORS: error: immediate operand must a number in the range [0, 255]
+@ CHECK-ERRORS: error: immediate operand must an even number in the range [0, 30]
+@ CHECK-ERRORS: error: immediate operand must a number in the range [0, 255]
+@ CHECK-ERRORS: error: immediate operand must an even number in the range [0, 30]
+@ CHECK-ERRORS: error: immediate operand must a number in the range [0, 255]
+@ CHECK-ERRORS: error: immediate operand must an even number in the range [0, 30]
@ CHECK-ERRORS: error: instruction requires: thumb2
@ CHECK-ERRORS: add sp, sp, #512
@ CHECK-ERRORS: ^
-@ CHECK-ERRORS: error: instruction requires: arm-mode
+@ CHECK-ERRORS: error: instruction requires: thumb2
@ CHECK-ERRORS: add r2, sp, #1024
@ CHECK-ERRORS: ^
# RUN: llvm-mc --disassemble %s -triple=armv7-apple-darwin9 -mcpu=cortex-a9 | FileCheck %s
-# CHECK: addpl r4, pc, #318767104
+# CHECK: addpl r4, pc, #76, #10
0x4c 0x45 0x8f 0x52
# CHECK: b #0
# CHECK: adc r1, r2, #983040
# CHECK: adc r1, r2, #15728640
# CHECK: adc r1, r2, #251658240
-# CHECK: adc r1, r2, #4026531840
-# CHECK: adc r1, r2, #4026531855
+# CHECK: adc r1, r2, #-268435456
+# CHECK: adc r1, r2, #-268435441
+# CHECK: adc r7, r8, #-2147483638
+# CHECK: adc r7, r8, #40, #2
# CHECK: adcs r1, r2, #3840
+# CHECK: adcs r7, r8, #40, #2
# CHECK: adcseq r1, r2, #3840
# CHECK: adceq r1, r2, #3840
0x0f 0x14 0xa2 0xe2
0x0f 0x12 0xa2 0xe2
0xff 0x12 0xa2 0xe2
+0x2a 0x71 0xa8 0xe2
+0x28 0x71 0xa8 0xe2
0x0f 0x1c 0xb2 0xe2
+0x28 0x71 0xb8 0xe2
0x0f 0x1c 0xb2 0x02
0x0f 0x1c 0xa2 0x02
# ADD
#------------------------------------------------------------------------------
# CHECK: add r4, r5, #61440
+# CHECK: add r7, r8, #-2147483638
+# CHECK: add r7, r8, #40, #2
# CHECK: add r4, r5, r6
# CHECK: add r4, r5, r6, lsl #5
# CHECK: add r4, r5, r6, lsr #5
# CHECK: add r4, r4, r5, rrx
0x0f 0x4a 0x85 0xe2
+0x2a 0x71 0x88 0xe2
+0x28 0x71 0x88 0xe2
0x06 0x40 0x85 0xe0
0x86 0x42 0x85 0xe0
0xa6 0x42 0x85 0xe0
0x65 0x40 0x84 0xe0
#------------------------------------------------------------------------------
+# ADDS
+#------------------------------------------------------------------------------
+# CHECK: adds r7, r8, #-2147483638
+# CHECK: adds r7, r8, #40, #2
+
+0x2a 0x71 0x98 0xe2
+0x28 0x71 0x98 0xe2
+
+#------------------------------------------------------------------------------
# ADR
#------------------------------------------------------------------------------
# CHECK: add r2, pc, #3
# AND
#------------------------------------------------------------------------------
# CHECK: and r10, r1, #15
+# CHECK: and r7, r8, #-2147483638
+# CHECK: and r7, r8, #40, #2
# CHECK: and r10, r1, r6
# CHECK: and r10, r1, r6, lsl #10
# CHECK: and r10, r1, r6, lsr #10
# CHECK: and r10, r10, r1, rrx
0x0f 0xa0 0x01 0xe2
+0x2a 0x71 0x08 0xe2
+0x28 0x71 0x08 0xe2
0x06 0xa0 0x01 0xe0
0x06 0xa5 0x01 0xe0
0x26 0xa5 0x01 0xe0
# BIC
#------------------------------------------------------------------------------
# CHECK: bic r10, r1, #15
+# CHECK: bic r7, r8, #-2147483638
+# CHECK: bic r7, r8, #40, #2
# CHECK: bic r10, r1, r6
# CHECK: bic r10, r1, r6, lsl #10
# CHECK: bic r10, r1, r6, lsr #10
# CHECK: bic r10, r10, r1, rrx
0x0f 0xa0 0xc1 0xe3
+0x2a 0x71 0xc8 0xe3
+0x28 0x71 0xc8 0xe3
0x06 0xa0 0xc1 0xe1
0x06 0xa5 0xc1 0xe1
0x26 0xa5 0xc1 0xe1
# CMN
#------------------------------------------------------------------------------
# CHECK: cmn r1, #15
+# CHECK: cmn r7, #40, #2
+# CHECK: cmn r7, #-2147483638
# CHECK: cmn r1, r6
# CHECK: cmn r1, r6, lsl #10
# CHECK: cmn r1, r6, lsr #10
# CHECK: cmn r1, r6, rrx
0x0f 0x00 0x71 0xe3
+0x28 0x01 0x77 0xe3
+0x2a 0x01 0x77 0xe3
0x06 0x00 0x71 0xe1
0x06 0x05 0x71 0xe1
0x26 0x05 0x71 0xe1
# CMP
#------------------------------------------------------------------------------
# CHECK: cmp r1, #15
+# CHECK: cmp r7, #40, #2
+# CHECK: cmp r7, #-2147483638
# CHECK: cmp r1, r6
# CHECK: cmp r1, r6, lsl #10
# CHECK: cmp r1, r6, lsr #10
# CHECK: cmp r1, r6, rrx
0x0f 0x00 0x51 0xe3
+0x28 0x01 0x57 0xe3
+0x2a 0x01 0x57 0xe3
0x06 0x00 0x51 0xe1
0x06 0x05 0x51 0xe1
0x26 0x05 0x51 0xe1
# EOR
#------------------------------------------------------------------------------
# CHECK: eor r4, r5, #61440
+# CHECK: eor r7, r8, #-2147483638
+# CHECK: eor r7, r8, #40, #2
# CHECK: eor r4, r5, r6
# CHECK: eor r4, r5, r6, lsl #5
# CHECK: eor r4, r5, r6, lsr #5
# CHECK: eor r4, r4, r5, rrx
0x0f 0x4a 0x25 0xe2
+0x2a 0x71 0x28 0xe2
+0x28 0x71 0x28 0xe2
0x06 0x40 0x25 0xe0
0x86 0x42 0x25 0xe0
0xa6 0x42 0x25 0xe0
# CHECK: mov r4, #4080
# CHECK: mov r5, #16711680
# CHECK: mov sp, #35
+# CHECK: mov r9, #240, #30
+# CHECK: mov r7, #-2147483638
+# CHECK: mov pc, #2147483658
# CHECK: movw r6, #65535
# CHECK: movw r9, #65535
# CHECK: movw sp, #1193
# CHECK: movs r3, #7
+# CHECK: movs r11, #99
+# CHECK: movs r11, #240, #30
# CHECK: moveq r4, #4080
# CHECK: movseq r5, #16711680
0xff 0x4e 0xa0 0xe3
0xff 0x58 0xa0 0xe3
0x23 0xd0 0xa0 0xe3
+0xf0 0x9f 0xa0 0xe3
+0x2a 0x71 0xa0 0xe3
+0x2a 0xf1 0xa0 0xe3
0xff 0x6f 0x0f 0xe3
0xff 0x9f 0x0f 0xe3
0xa9 0xd4 0x00 0xe3
0x07 0x30 0xb0 0xe3
+0x63 0xb0 0xb0 0xe3
+0xf0 0xbf 0xb0 0xe3
0xff 0x4e 0xa0 0x03
0xff 0x58 0xb0 0x03
# CHECK: msr SPSR_fc, #5
# CHECK: msr SPSR_fsxc, #5
# CHECK: msr CPSR_fsxc, #5
+# CHECK: msr APSR_nzcvq, #2147483658
+# CHECK: msr SPSR_fsxc, #40, #2
0x05 0xf0 0x29 0xe3
0x05 0xf0 0x24 0xe3
0x05 0xf0 0x69 0xe3
0x05 0xf0 0x6f 0xe3
0x05 0xf0 0x2f 0xe3
+0x2a 0xf1 0x28 0xe3
+0x28 0xf1 0x6f 0xe3
# CHECK: msr CPSR_fc, r0
# CHECK: msr APSR_g, r0
# CHECK: mvn r3, #7
# CHECK: mvn r4, #4080
# CHECK: mvn r5, #16711680
+# CHECK: mvn r7, #40, #2
+# CHECK: mvn r7, #-2147483638
# CHECK: mvns r3, #7
+# CHECK: mvns r11, #240, #30
+# CHECK: mvns r11, #-2147483638
# CHECK: mvneq r4, #4080
# CHECK: mvnseq r5, #16711680
0x07 0x30 0xe0 0xe3
0xff 0x4e 0xe0 0xe3
0xff 0x58 0xe0 0xe3
+0x28 0x71 0xe0 0xe3
+0x2a 0x71 0xe0 0xe3
0x07 0x30 0xf0 0xe3
+0xf0 0xbf 0xf0 0xe3
+0x2a 0xb1 0xf0 0xe3
0xff 0x4e 0xe0 0x03
0xff 0x58 0xf0 0x03
# ORR
#------------------------------------------------------------------------------
# CHECK: orr r4, r5, #61440
+# CHECK: orr r7, r8, #-2147483638
+# CHECK: orr r7, r8, #40, #2
# CHECK: orr r4, r5, r6
# CHECK: orr r4, r5, r6, lsl #5
# CHECK: orr r4, r5, r6, lsr #5
# CHECK: orr r4, r4, r5, rrx
0x0f 0x4a 0x85 0xe3
+0x2a 0x71 0x88 0xe3
+0x28 0x71 0x88 0xe3
0x06 0x40 0x85 0xe1
0x86 0x42 0x85 0xe1
0xa6 0x42 0x85 0xe1
# RSB
#------------------------------------------------------------------------------
# CHECK: rsb r4, r5, #61440
+# CHECK: rsb r7, r8, #-2147483638
+# CHECK: rsb r7, r8, #40, #2
# CHECK: rsb r4, r5, r6
# CHECK: rsb r4, r5, r6, lsl #5
# CHECK: rsblo r4, r5, r6, lsr #5
# CHECK: rsb r4, r4, r5, rrx
0x0f 0x4a 0x65 0xe2
+0x2a 0x71 0x68 0xe2
+0x28 0x71 0x68 0xe2
0x06 0x40 0x65 0xe0
0x86 0x42 0x65 0xe0
0xa6 0x42 0x65 0x30
0x65 0x40 0x64 0xe0
#------------------------------------------------------------------------------
+# RSBS
+#------------------------------------------------------------------------------
+# CHECK: rsbs r7, r8, #-2147483638
+# CHECK: rsbs r7, r8, #40, #2
+
+0x2a 0x71 0x78 0xe2
+0x28 0x71 0x78 0xe2
+
+#------------------------------------------------------------------------------
# RSC
#------------------------------------------------------------------------------
# CHECK: rsc r4, r5, #61440
+# CHECK: rsc r7, r8, #-2147483638
+# CHECK: rsc r7, r8, #40, #2
# CHECK: rsc r4, r5, r6
# CHECK: rsc r4, r5, r6, lsl #5
# CHECK: rsclo r4, r5, r6, lsr #5
# CHECK: rsc r6, r6, r7, ror r9
0x0f 0x4a 0xe5 0xe2
+0x2a 0x71 0xe8 0xe2
+0x28 0x71 0xe8 0xe2
0x06 0x40 0xe5 0xe0
0x86 0x42 0xe5 0xe0
0xa6 0x42 0xe5 0x30
# SBC
#------------------------------------------------------------------------------
# CHECK: sbc r4, r5, #61440
+# CHECK: sbc r7, r8, #-2147483638
+# CHECK: sbc r7, r8, #40, #2
# CHECK: sbc r4, r5, r6
# CHECK: sbc r4, r5, r6, lsl #5
# CHECK: sbc r4, r5, r6, lsr #5
# CHECK: sbc r6, r6, r7, ror r9
0x0f 0x4a 0xc5 0xe2
+0x2a 0x71 0xc8 0xe2
+0x28 0x71 0xc8 0xe2
0x06 0x40 0xc5 0xe0
0x86 0x42 0xc5 0xe0
0xa6 0x42 0xc5 0xe0
# SUB
#------------------------------------------------------------------------------
# CHECK: sub r4, r5, #61440
+# CHECK: sub r7, r8, #-2147483638
+# CHECK: sub r7, r8, #40, #2
# CHECK: sub r4, r5, r6
# CHECK: sub r4, r5, r6, lsl #5
# CHECK: sub r4, r5, r6, lsr #5
# CHECK: sub r6, r6, r7, ror r9
0x0f 0x4a 0x45 0xe2
+0x2a 0x71 0x48 0xe2
+0x28 0x71 0x48 0xe2
0x06 0x40 0x45 0xe0
0x86 0x42 0x45 0xe0
0xa6 0x42 0x45 0xe0
0x57 0x69 0x46 0xe0
0x77 0x69 0x46 0xe0
+#------------------------------------------------------------------------------
+# SUBS
+#------------------------------------------------------------------------------
+# CHECK: subs r7, r8, #-2147483638
+# CHECK: subs r7, r8, #40, #2
+
+0x2a 0x71 0x58 0xe2
+0x28 0x71 0x58 0xe2
#------------------------------------------------------------------------------
# SVC
# TEQ
#------------------------------------------------------------------------------
# CHECK: teq r5, #61440
+# CHECK: teq r7, #-2147483638
+# CHECK: teq r7, #40, #2
# CHECK: teq r4, r5
# CHECK: teq r4, r5, lsl #5
# CHECK: teq r4, r5, lsr #5
# CHECK: teq r6, r7, ror r9
0x0f 0x0a 0x35 0xe3
+0x2a 0x01 0x37 0xe3
+0x28 0x01 0x37 0xe3
0x05 0x00 0x34 0xe1
0x85 0x02 0x34 0xe1
0xa5 0x02 0x34 0xe1
# TST
#------------------------------------------------------------------------------
# CHECK: tst r5, #61440
+# CHECK: tst r7, #-2147483638
+# CHECK: tst r7, #40, #2
# CHECK: tst r4, r5
# CHECK: tst r4, r5, lsl #5
# CHECK: tst r4, r5, lsr #5
# CHECK: tst r6, r7, ror r9
0x0f 0x0a 0x15 0xe3
+0x2a 0x01 0x17 0xe3
+0x28 0x01 0x17 0xe3
0x05 0x00 0x14 0xe1
0x85 0x02 0x14 0xe1
0xa5 0x02 0x14 0xe1