OSDN Git Service

ARM: dts: microchip: split interrupts per cells
authorKrzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Sun, 30 Jul 2023 11:15:41 +0000 (13:15 +0200)
committerClaudiu Beznea <claudiu.beznea@tuxon.dev>
Wed, 2 Aug 2023 04:44:24 +0000 (07:44 +0300)
Each interrupt should be in its own cell.  This is much more readable.

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20230730111542.98238-1-krzysztof.kozlowski@linaro.org
Signed-off-by: Claudiu Beznea <claudiu.beznea@tuxon.dev>
arch/arm/boot/dts/microchip/at91rm9200.dtsi
arch/arm/boot/dts/microchip/at91sam9260.dtsi
arch/arm/boot/dts/microchip/sama5d2.dtsi
arch/arm/boot/dts/microchip/sama7g5.dtsi

index 37b500f..16c675e 100644 (file)
                                #address-cells = <1>;
                                #size-cells = <0>;
                                reg = <0xfffa0000 0x100>;
-                               interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0
-                                             18 IRQ_TYPE_LEVEL_HIGH 0
-                                             19 IRQ_TYPE_LEVEL_HIGH 0>;
+                               interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0>,
+                                            <18 IRQ_TYPE_LEVEL_HIGH 0>,
+                                            <19 IRQ_TYPE_LEVEL_HIGH 0>;
                                clocks = <&pmc PMC_TYPE_PERIPHERAL 17>, <&pmc PMC_TYPE_PERIPHERAL 18>, <&pmc PMC_TYPE_PERIPHERAL 19>, <&slow_xtal>;
                                clock-names = "t0_clk", "t1_clk", "t2_clk", "slow_clk";
                        };
                                #address-cells = <1>;
                                #size-cells = <0>;
                                reg = <0xfffa4000 0x100>;
-                               interrupts = <20 IRQ_TYPE_LEVEL_HIGH 0
-                                             21 IRQ_TYPE_LEVEL_HIGH 0
-                                             22 IRQ_TYPE_LEVEL_HIGH 0>;
+                               interrupts = <20 IRQ_TYPE_LEVEL_HIGH 0>,
+                                            <21 IRQ_TYPE_LEVEL_HIGH 0>,
+                                            <22 IRQ_TYPE_LEVEL_HIGH 0>;
                                clocks = <&pmc PMC_TYPE_PERIPHERAL 20>, <&pmc PMC_TYPE_PERIPHERAL 21>, <&pmc PMC_TYPE_PERIPHERAL 22>, <&slow_xtal>;
                                clock-names = "t0_clk", "t1_clk", "t2_clk", "slow_clk";
                        };
index 27b4a21..e56d554 100644 (file)
                                #address-cells = <1>;
                                #size-cells = <0>;
                                reg = <0xfffa0000 0x100>;
-                               interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0
-                                             18 IRQ_TYPE_LEVEL_HIGH 0
-                                             19 IRQ_TYPE_LEVEL_HIGH 0>;
+                               interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0>,
+                                            <18 IRQ_TYPE_LEVEL_HIGH 0>,
+                                            <19 IRQ_TYPE_LEVEL_HIGH 0>;
                                clocks = <&pmc PMC_TYPE_PERIPHERAL 17>, <&pmc PMC_TYPE_PERIPHERAL 18>, <&pmc PMC_TYPE_PERIPHERAL 19>, <&pmc PMC_TYPE_CORE PMC_SLOW>;
                                clock-names = "t0_clk", "t1_clk", "t2_clk", "slow_clk";
                        };
                                #address-cells = <1>;
                                #size-cells = <0>;
                                reg = <0xfffdc000 0x100>;
-                               interrupts = <26 IRQ_TYPE_LEVEL_HIGH 0
-                                             27 IRQ_TYPE_LEVEL_HIGH 0
-                                             28 IRQ_TYPE_LEVEL_HIGH 0>;
+                               interrupts = <26 IRQ_TYPE_LEVEL_HIGH 0>,
+                                            <27 IRQ_TYPE_LEVEL_HIGH 0>,
+                                            <28 IRQ_TYPE_LEVEL_HIGH 0>;
                                clocks = <&pmc PMC_TYPE_PERIPHERAL 26>, <&pmc PMC_TYPE_PERIPHERAL 27>, <&pmc PMC_TYPE_PERIPHERAL 28>, <&pmc PMC_TYPE_CORE PMC_SLOW>;
                                clock-names = "t0_clk", "t1_clk", "t2_clk", "slow_clk";
                        };
index daeeb24..5f8e297 100644 (file)
                        macb0: ethernet@f8008000 {
                                compatible = "atmel,sama5d2-gem";
                                reg = <0xf8008000 0x1000>;
-                               interrupts = <5  IRQ_TYPE_LEVEL_HIGH 3          /* Queue 0 */
-                                             66 IRQ_TYPE_LEVEL_HIGH 3          /* Queue 1 */
-                                             67 IRQ_TYPE_LEVEL_HIGH 3>;        /* Queue 2 */
+                               interrupts = <5  IRQ_TYPE_LEVEL_HIGH 3>,        /* Queue 0 */
+                                            <66 IRQ_TYPE_LEVEL_HIGH 3>,        /* Queue 1 */
+                                            <67 IRQ_TYPE_LEVEL_HIGH 3>;        /* Queue 2 */
                                clocks = <&pmc PMC_TYPE_PERIPHERAL 5>, <&pmc PMC_TYPE_PERIPHERAL 5>;
                                clock-names = "hclk", "pclk";
                                status = "disabled";
index 9642a42..269e0a3 100644 (file)
                        compatible = "bosch,m_can";
                        reg = <0xe0828000 0x100>, <0x100000 0x7800>;
                        reg-names = "m_can", "message_ram";
-                       interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH
-                                     GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
+                       interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
                        interrupt-names = "int0", "int1";
                        clocks = <&pmc PMC_TYPE_PERIPHERAL 61>, <&pmc PMC_TYPE_GCK 61>;
                        clock-names = "hclk", "cclk";
                        compatible = "bosch,m_can";
                        reg = <0xe082c000 0x100>, <0x100000 0xbc00>;
                        reg-names = "m_can", "message_ram";
-                       interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH
-                                     GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
+                       interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
                        interrupt-names = "int0", "int1";
                        clocks = <&pmc PMC_TYPE_PERIPHERAL 62>, <&pmc PMC_TYPE_GCK 62>;
                        clock-names = "hclk", "cclk";
                        compatible = "bosch,m_can";
                        reg = <0xe0830000 0x100>, <0x100000 0x10000>;
                        reg-names = "m_can", "message_ram";
-                       interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH
-                                     GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
+                       interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
                        interrupt-names = "int0", "int1";
                        clocks = <&pmc PMC_TYPE_PERIPHERAL 63>, <&pmc PMC_TYPE_GCK 63>;
                        clock-names = "hclk", "cclk";
                        compatible = "bosch,m_can";
                        reg = <0xe0834000 0x100>, <0x110000 0x4400>;
                        reg-names = "m_can", "message_ram";
-                       interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH
-                                     GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
+                       interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
                        interrupt-names = "int0", "int1";
                        clocks = <&pmc PMC_TYPE_PERIPHERAL 64>, <&pmc PMC_TYPE_GCK 64>;
                        clock-names = "hclk", "cclk";
                        compatible = "bosch,m_can";
                        reg = <0xe0838000 0x100>, <0x110000 0x8800>;
                        reg-names = "m_can", "message_ram";
-                       interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH
-                                     GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
+                       interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
                        interrupt-names = "int0", "int1";
                        clocks = <&pmc PMC_TYPE_PERIPHERAL 65>, <&pmc PMC_TYPE_GCK 65>;
                        clock-names = "hclk", "cclk";
                        compatible = "bosch,m_can";
                        reg = <0xe083c000 0x100>, <0x110000 0xcc00>;
                        reg-names = "m_can", "message_ram";
-                       interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH
-                                     GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>;
+                       interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>;
                        interrupt-names = "int0", "int1";
                        clocks = <&pmc PMC_TYPE_PERIPHERAL 66>, <&pmc PMC_TYPE_GCK 66>;
                        clock-names = "hclk", "cclk";
                gmac0: ethernet@e2800000 {
                        compatible = "microchip,sama7g5-gem";
                        reg = <0xe2800000 0x1000>;
-                       interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH
-                                     GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH
-                                     GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH
-                                     GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH
-                                     GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH
-                                     GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
+                       interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
                        clocks = <&pmc PMC_TYPE_PERIPHERAL 51>, <&pmc PMC_TYPE_PERIPHERAL 51>, <&pmc PMC_TYPE_GCK 51>, <&pmc PMC_TYPE_GCK 53>;
                        clock-names = "pclk", "hclk", "tx_clk", "tsu_clk";
                        assigned-clocks = <&pmc PMC_TYPE_GCK 51>;
                gmac1: ethernet@e2804000 {
                        compatible = "microchip,sama7g5-emac";
                        reg = <0xe2804000 0x1000>;
-                       interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH
-                                     GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
+                       interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
                        clocks = <&pmc PMC_TYPE_PERIPHERAL 52>, <&pmc PMC_TYPE_PERIPHERAL 52>;
                        clock-names = "pclk", "hclk";
                        status = "disabled";