For M profile we must clear the exclusive monitor on reset, exception
entry and exception exit. We weren't doing any of these things; fix
this bug.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@xilinx.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id:
1505137930-13255-3-git-send-email-peter.maydell@linaro.org
env->regs[15] = 0xFFFF0000;
}
+ /* M profile requires that reset clears the exclusive monitor;
+ * A profile does not, but clearing it makes more sense than having it
+ * set with an exclusive access on address zero.
+ */
+ arm_clear_exclusive(env);
+
env->vfp.xregs[ARM_VFP_FPEXC] = 0;
#endif
armv7m_nvic_acknowledge_irq(env->nvic);
switch_v7m_sp(env, 0);
+ arm_clear_exclusive(env);
/* Clear IT bits */
env->condexec_bits = 0;
env->regs[14] = lr;
}
/* Otherwise, we have a successful exception exit. */
+ arm_clear_exclusive(env);
qemu_log_mask(CPU_LOG_INT, "...successful exception return\n");
}
#endif
/**
+ * arm_clear_exclusive: clear the exclusive monitor
+ * @env: CPU env
+ * Clear the CPU's exclusive monitor, like the guest CLREX instruction.
+ */
+static inline void arm_clear_exclusive(CPUARMState *env)
+{
+ env->exclusive_addr = -1;
+}
+
+/**
* ARMMMUFaultInfo: Information describing an ARM MMU Fault
* @s2addr: Address that caused a fault at stage 2
* @stage2: True if we faulted at stage 2
aarch64_save_sp(env, cur_el);
- env->exclusive_addr = -1;
+ arm_clear_exclusive(env);
/* We must squash the PSTATE.SS bit to zero unless both of the
* following hold: