Make subs and adds alter flags when rn is an immediate

Change-Id: I70e0d78f155bf806222ad12a324dbd8c8fe575a1

diff --git a/compiler/utils/arm/assembler_thumb2.cc b/compiler/utils/arm/assembler_thumb2.cc
index 6d0571e..e95db0d 100644 (file)
--- a/compiler/utils/arm/assembler_thumb2.cc
+++ b/compiler/utils/arm/assembler_thumb2.cc
@@ -825,10 +825,12 @@ void Thumb2Assembler::Emit32BitDataProcessing(Condition cond ATTRIBUTE_UNUSED,
   if (so.IsImmediate()) {
     // Check special cases.
     if ((opcode == SUB || opcode == ADD) && (so.GetImmediate() < (1u << 12))) {
-      if (opcode == SUB) {
-        thumb_opcode = 5U /* 0b0101 */;
-      } else {
-        thumb_opcode = 0;
+      if (!set_cc) {
+        if (opcode == SUB) {
+          thumb_opcode = 5U;
+        } else if (opcode == ADD) {
+          thumb_opcode = 0U;
+        }
       }
       uint32_t imm = so.GetImmediate();
 
@@ -836,13 +838,14 @@ void Thumb2Assembler::Emit32BitDataProcessing(Condition cond ATTRIBUTE_UNUSED,
       uint32_t imm3 = (imm >> 8) & 7U /* 0b111 */;
       uint32_t imm8 = imm & 0xff;
 
-      encoding = B31 | B30 | B29 | B28 | B25 |
-           thumb_opcode << 21 |
-           rn << 16 |
-           rd << 8 |
-           i << 26 |
-           imm3 << 12 |
-           imm8;
+      encoding = B31 | B30 | B29 | B28 |
+          (set_cc ? B20 : B25) |
+          thumb_opcode << 21 |
+          rn << 16 |
+          rd << 8 |
+          i << 26 |
+          imm3 << 12 |
+          imm8;
     } else {
       // Modified immediate.
       uint32_t imm = ModifiedImmediate(so.encodingThumb());
@@ -852,19 +855,19 @@ void Thumb2Assembler::Emit32BitDataProcessing(Condition cond ATTRIBUTE_UNUSED,
       }
       encoding = B31 | B30 | B29 | B28 |
           thumb_opcode << 21 |
-          (set_cc ? 1 : 0) << 20 |
+          (set_cc ? B20 : 0) |
           rn << 16 |
           rd << 8 |
           imm;
     }
   } else if (so.IsRegister()) {
-     // Register (possibly shifted)
-     encoding = B31 | B30 | B29 | B27 | B25 |
-         thumb_opcode << 21 |
-         (set_cc ? 1 : 0) << 20 |
-         rn << 16 |
-         rd << 8 |
-         so.encodingThumb();
+    // Register (possibly shifted)
+    encoding = B31 | B30 | B29 | B27 | B25 |
+        thumb_opcode << 21 |
+        (set_cc ? B20 : 0) |
+        rn << 16 |
+        rd << 8 |
+        so.encodingThumb();
   }
   Emit32(encoding);
 }

diff --git a/compiler/utils/arm/assembler_thumb2_test.cc b/compiler/utils/arm/assembler_thumb2_test.cc
index ebea9d4..813996b 100644 (file)
--- a/compiler/utils/arm/assembler_thumb2_test.cc
+++ b/compiler/utils/arm/assembler_thumb2_test.cc
@@ -227,4 +227,24 @@ TEST_F(AssemblerThumb2Test, eor) {
   DriverStr(expected, "abs");
 }
 
+TEST_F(AssemblerThumb2Test, sub) {
+  __ subs(arm::R1, arm::R0, arm::ShifterOperand(42));
+  __ sub(arm::R1, arm::R0, arm::ShifterOperand(42));
+
+  const char* expected =
+      "subs r1, r0, #42\n"
+      "subw r1, r0, #42\n";
+  DriverStr(expected, "sub");
+}
+
+TEST_F(AssemblerThumb2Test, add) {
+  __ adds(arm::R1, arm::R0, arm::ShifterOperand(42));
+  __ add(arm::R1, arm::R0, arm::ShifterOperand(42));
+
+  const char* expected =
+      "adds r1, r0, #42\n"
+      "addw r1, r0, #42\n";
+  DriverStr(expected, "add");
+}
+
 }  // namespace art