drm/i915: Rename VRR_CTL reg fields

Give the pipeline full line count bits more descriptive names

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
Reviewed-by: Manasi Navare <manasi.d.navare@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210122232647.22688-9-manasi.d.navare@intel.com

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 8b9bbc6..e7e41a3 100644 (file)
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4346,13 +4346,13 @@ enum {
 #define _TRANS_VRR_CTL_B               0x61420
 #define _TRANS_VRR_CTL_C               0x62420
 #define _TRANS_VRR_CTL_D               0x63420
-#define TRANS_VRR_CTL(trans)           _MMIO_TRANS2(trans, _TRANS_VRR_CTL_A)
-#define   VRR_CTL_VRR_ENABLE           REG_BIT(31)
-#define   VRR_CTL_IGN_MAX_SHIFT                REG_BIT(30)
-#define   VRR_CTL_FLIP_LINE_EN         REG_BIT(29)
-#define   VRR_CTL_LINE_COUNT_MASK      REG_GENMASK(10, 3)
-#define   VRR_CTL_LINE_COUNT(x)                REG_FIELD_PREP(VRR_CTL_LINE_COUNT_MASK, (x))
-#define   VRR_CTL_SW_FULLLINE_COUNT    REG_BIT(0)
+#define TRANS_VRR_CTL(trans)                   _MMIO_TRANS2(trans, _TRANS_VRR_CTL_A)
+#define   VRR_CTL_VRR_ENABLE                   REG_BIT(31)
+#define   VRR_CTL_IGN_MAX_SHIFT                        REG_BIT(30)
+#define   VRR_CTL_FLIP_LINE_EN                 REG_BIT(29)
+#define   VRR_CTL_PIPELINE_FULL_MASK           REG_GENMASK(10, 3)
+#define   VRR_CTL_PIPELINE_FULL(x)             REG_FIELD_PREP(VRR_CTL_PIPELINE_FULL_MASK, (x))
+#define   VRR_CTL_PIPELINE_FULL_OVERRIDE       REG_BIT(0)
 
 #define _TRANS_VRR_VMAX_A              0x60424
 #define _TRANS_VRR_VMAX_B              0x61424