PCI: qcom: Change duplicate PCI reset to phy reset

The deinit issues reset_control_assert for PCI twice and does not contain
phy reset.

Link: https://lore.kernel.org/r/20200615210608.21469-4-ansuelsmth@gmail.com
Signed-off-by: Abhishek Sahu <absahu@codeaurora.org>
Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Acked-by: Stanimir Varbanov <svarbanov@mm-sol.com>

diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c
index fa0bf65..bae5158 100644 (file)
--- a/drivers/pci/controller/dwc/pcie-qcom.c
+++ b/drivers/pci/controller/dwc/pcie-qcom.c
@@ -280,14 +280,14 @@ static void qcom_pcie_deinit_2_1_0(struct qcom_pcie *pcie)
 {
        struct qcom_pcie_resources_2_1_0 *res = &pcie->res.v2_1_0;
 
+       clk_disable_unprepare(res->phy_clk);
        reset_control_assert(res->pci_reset);
        reset_control_assert(res->axi_reset);
        reset_control_assert(res->ahb_reset);
        reset_control_assert(res->por_reset);
-       reset_control_assert(res->pci_reset);
+       reset_control_assert(res->phy_reset);
        clk_disable_unprepare(res->iface_clk);
        clk_disable_unprepare(res->core_clk);
-       clk_disable_unprepare(res->phy_clk);
        clk_disable_unprepare(res->aux_clk);
        clk_disable_unprepare(res->ref_clk);
        regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies);
@@ -325,12 +325,6 @@ static int qcom_pcie_init_2_1_0(struct qcom_pcie *pcie)
                goto err_clk_core;
        }
 
-       ret = clk_prepare_enable(res->phy_clk);
-       if (ret) {
-               dev_err(dev, "cannot prepare/enable phy clock\n");
-               goto err_clk_phy;
-       }
-
        ret = clk_prepare_enable(res->aux_clk);
        if (ret) {
                dev_err(dev, "cannot prepare/enable aux clock\n");
@@ -383,6 +377,12 @@ static int qcom_pcie_init_2_1_0(struct qcom_pcie *pcie)
                return ret;
        }
 
+       ret = clk_prepare_enable(res->phy_clk);
+       if (ret) {
+               dev_err(dev, "cannot prepare/enable phy clock\n");
+               goto err_deassert_ahb;
+       }
+
        /* wait for clock acquisition */
        usleep_range(1000, 1500);
 
@@ -400,8 +400,6 @@ err_deassert_ahb:
 err_clk_ref:
        clk_disable_unprepare(res->aux_clk);
 err_clk_aux:
-       clk_disable_unprepare(res->phy_clk);
-err_clk_phy:
        clk_disable_unprepare(res->core_clk);
 err_clk_core:
        clk_disable_unprepare(res->iface_clk);