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RDMA/hns: Initialize the PCI device for hip08 RoCE
authorWei Hu(Xavier) <xavier.huwei@huawei.com>
Wed, 30 Aug 2017 09:23:01 +0000 (17:23 +0800)
committerDoug Ledford <dledford@redhat.com>
Wed, 27 Sep 2017 12:34:55 +0000 (08:34 -0400)
The hip08 RoCE engine is a PCI device. This patch mainly
obtains some information of PCI device for hip08 RoCE from
hns3 NIC driver in the initialization.

Signed-off-by: Lijun Ou <oulijun@huawei.com>
Signed-off-by: Shaobo Xu <xushaobo2@huawei.com>
Signed-off-by: Wei Hu (Xavier) <xavier.huwei@huawei.com>
Signed-off-by: Doug Ledford <dledford@redhat.com>
drivers/infiniband/hw/hns/Kconfig
drivers/infiniband/hw/hns/Makefile
drivers/infiniband/hw/hns/hns_roce_device.h
drivers/infiniband/hw/hns/hns_roce_hw_v2.c [new file with mode: 0644]

index 37e33e5..fddb5fd 100644 (file)
@@ -19,3 +19,13 @@ config INFINIBAND_HNS_HIP06
 
          To compile this driver as a module, choose M here: the module
          will be called hns-roce-hw-v1.
+
+config INFINIBAND_HNS_HIP08
+       tristate "Hisilicon Hip08 Family RoCE support"
+       depends on INFINIBAND_HNS && PCI && HNS3
+       ---help---
+         RoCE driver support for Hisilicon RoCE engine in Hisilicon Hip08 SoC.
+         The RoCE engine is a PCI device.
+
+         To compile this driver as a module, choose M here: the module
+         will be called hns-roce-hw-v2.
index 806ac4e..ff426a6 100644 (file)
@@ -2,9 +2,13 @@
 # Makefile for the Hisilicon RoCE drivers.
 #
 
+ccflags-y :=  -Idrivers/net/ethernet/hisilicon/hns3
+
 obj-$(CONFIG_INFINIBAND_HNS) += hns-roce.o
 hns-roce-objs := hns_roce_main.o hns_roce_cmd.o hns_roce_eq.o hns_roce_pd.o \
        hns_roce_ah.o hns_roce_hem.o hns_roce_mr.o hns_roce_qp.o \
        hns_roce_cq.o hns_roce_alloc.o
 obj-$(CONFIG_INFINIBAND_HNS_HIP06) += hns-roce-hw-v1.o
 hns-roce-hw-v1-objs := hns_roce_hw_v1.o
+obj-$(CONFIG_INFINIBAND_HNS_HIP08) += hns-roce-hw-v2.o
+hns-roce-hw-v2-objs := hns_roce_hw_v2.o
index aa9281e..3132b68 100644 (file)
@@ -540,6 +540,8 @@ struct hns_roce_hw {
 struct hns_roce_dev {
        struct ib_device        ib_dev;
        struct platform_device  *pdev;
+       struct pci_dev          *pci_dev;
+       struct device           *dev;
        struct hns_roce_uar     priv_uar;
        const char              *irq_names[HNS_ROCE_MAX_IRQ_NUM];
        spinlock_t              sm_lock;
diff --git a/drivers/infiniband/hw/hns/hns_roce_hw_v2.c b/drivers/infiniband/hw/hns/hns_roce_hw_v2.c
new file mode 100644 (file)
index 0000000..b35c72d
--- /dev/null
@@ -0,0 +1,151 @@
+/*
+ * Copyright (c) 2016-2017 Hisilicon Limited.
+ *
+ * This software is available to you under a choice of one of two
+ * licenses.  You may choose to be licensed under the terms of the GNU
+ * General Public License (GPL) Version 2, available from the file
+ * COPYING in the main directory of this source tree, or the
+ * OpenIB.org BSD license below:
+ *
+ *     Redistribution and use in source and binary forms, with or
+ *     without modification, are permitted provided that the following
+ *     conditions are met:
+ *
+ *      - Redistributions of source code must retain the above
+ *        copyright notice, this list of conditions and the following
+ *        disclaimer.
+ *
+ *      - Redistributions in binary form must reproduce the above
+ *        copyright notice, this list of conditions and the following
+ *        disclaimer in the documentation and/or other materials
+ *        provided with the distribution.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
+ * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
+ * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ */
+
+#include <linux/acpi.h>
+#include <linux/etherdevice.h>
+#include <linux/interrupt.h>
+#include <linux/kernel.h>
+#include <rdma/ib_umem.h>
+
+#include "hnae3.h"
+#include "hns_roce_common.h"
+#include "hns_roce_device.h"
+#include "hns_roce_cmd.h"
+#include "hns_roce_hem.h"
+
+static const struct hns_roce_hw hns_roce_hw_v2;
+
+static const struct pci_device_id hns_roce_hw_v2_pci_tbl[] = {
+       {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA), 0},
+       {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA_MACSEC), 0},
+       {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_RDMA_MACSEC), 0},
+       /* required last entry */
+       {0, }
+};
+
+static int hns_roce_hw_v2_get_cfg(struct hns_roce_dev *hr_dev,
+                                 struct hnae3_handle *handle)
+{
+       const struct pci_device_id *id;
+
+       id = pci_match_id(hns_roce_hw_v2_pci_tbl, hr_dev->pci_dev);
+       if (!id) {
+               dev_err(hr_dev->dev, "device is not compatible!\n");
+               return -ENXIO;
+       }
+
+       hr_dev->hw = &hns_roce_hw_v2;
+
+       /* Get info from NIC driver. */
+       hr_dev->reg_base = handle->rinfo.roce_io_base;
+       hr_dev->caps.num_ports = 1;
+       hr_dev->iboe.netdevs[0] = handle->rinfo.netdev;
+       hr_dev->iboe.phy_port[0] = 0;
+
+       /* cmd issue mode: 0 is poll, 1 is event */
+       hr_dev->cmd_mod = 0;
+       hr_dev->loop_idc = 0;
+
+       return 0;
+}
+
+static int hns_roce_hw_v2_init_instance(struct hnae3_handle *handle)
+{
+       struct hns_roce_dev *hr_dev;
+       int ret;
+
+       hr_dev = (struct hns_roce_dev *)ib_alloc_device(sizeof(*hr_dev));
+       if (!hr_dev)
+               return -ENOMEM;
+
+       hr_dev->pci_dev = handle->pdev;
+       hr_dev->dev = &handle->pdev->dev;
+       handle->priv = hr_dev;
+
+       ret = hns_roce_hw_v2_get_cfg(hr_dev, handle);
+       if (ret) {
+               dev_err(hr_dev->dev, "Get Configuration failed!\n");
+               goto error_failed_get_cfg;
+       }
+
+       ret = hns_roce_init(hr_dev);
+       if (ret) {
+               dev_err(hr_dev->dev, "RoCE Engine init failed!\n");
+               goto error_failed_get_cfg;
+       }
+
+       return 0;
+
+error_failed_get_cfg:
+       ib_dealloc_device(&hr_dev->ib_dev);
+
+       return ret;
+}
+
+static void hns_roce_hw_v2_uninit_instance(struct hnae3_handle *handle,
+                                          bool reset)
+{
+       struct hns_roce_dev *hr_dev = (struct hns_roce_dev *)handle->priv;
+
+       hns_roce_exit(hr_dev);
+       ib_dealloc_device(&hr_dev->ib_dev);
+}
+
+static const struct hnae3_client_ops hns_roce_hw_v2_ops = {
+       .init_instance = hns_roce_hw_v2_init_instance,
+       .uninit_instance = hns_roce_hw_v2_uninit_instance,
+};
+
+static struct hnae3_client hns_roce_hw_v2_client = {
+       .name = "hns_roce_hw_v2",
+       .type = HNAE3_CLIENT_ROCE,
+       .ops = &hns_roce_hw_v2_ops,
+};
+
+static int __init hns_roce_hw_v2_init(void)
+{
+       return hnae3_register_client(&hns_roce_hw_v2_client);
+}
+
+static void __exit hns_roce_hw_v2_exit(void)
+{
+       hnae3_unregister_client(&hns_roce_hw_v2_client);
+}
+
+module_init(hns_roce_hw_v2_init);
+module_exit(hns_roce_hw_v2_exit);
+
+MODULE_LICENSE("Dual BSD/GPL");
+MODULE_AUTHOR("Wei Hu <xavier.huwei@huawei.com>");
+MODULE_AUTHOR("Lijun Ou <oulijun@huawei.com>");
+MODULE_AUTHOR("Shaobo Xu <xushaobo2@huawei.com>");
+MODULE_DESCRIPTION("Hisilicon Hip08 Family RoCE Driver");