tcg_temp_free(temp2);
}
+static void gen_swapmsk(DisasContext *ctx, int reg, TCGv ea)
+{
+ TCGv temp = tcg_temp_new();
+ TCGv temp2 = tcg_temp_new();
+ TCGv temp3 = tcg_temp_new();
+
+ tcg_gen_qemu_ld_tl(temp, ea, ctx->mem_idx, MO_LEUL);
+ tcg_gen_and_tl(temp2, cpu_gpr_d[reg], cpu_gpr_d[reg+1]);
+ tcg_gen_andc_tl(temp3, temp, cpu_gpr_d[reg+1]);
+ tcg_gen_or_tl(temp2, temp2, temp3);
+ tcg_gen_qemu_st_tl(temp2, ea, ctx->mem_idx, MO_LEUL);
+ tcg_gen_mov_tl(cpu_gpr_d[reg], temp);
+
+ tcg_temp_free(temp);
+ tcg_temp_free(temp2);
+ tcg_temp_free(temp3);
+}
+
+
/* We generate loads and store to core special function register (csfr) through
the function gen_mfcr and gen_mtcr. To handle access permissions, we use 3
makros R, A and E, which allow read-only, all and endinit protected access.
tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
gen_cmpswap(ctx, r1, cpu_gpr_a[r2]);
break;
+ case OPC2_32_BO_SWAPMSK_W_SHORTOFF:
+ tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10);
+ gen_swapmsk(ctx, r1, temp);
+ break;
+ case OPC2_32_BO_SWAPMSK_W_POSTINC:
+ gen_swapmsk(ctx, r1, cpu_gpr_a[r2]);
+ tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
+ break;
+ case OPC2_32_BO_SWAPMSK_W_PREINC:
+ tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
+ gen_swapmsk(ctx, r1, cpu_gpr_a[r2]);
+ break;
}
tcg_temp_free(temp);
tcg_temp_free(temp2);
gen_cmpswap(ctx, r1, temp2);
gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3);
break;
+ case OPC2_32_BO_SWAPMSK_W_BR:
+ gen_swapmsk(ctx, r1, temp2);
+ gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]);
+ break;
+ case OPC2_32_BO_SWAPMSK_W_CIRC:
+ gen_swapmsk(ctx, r1, temp2);
+ gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3);
+ break;
}
tcg_temp_free(temp);
OPC2_32_BO_CMPSWAP_W_SHORTOFF = 0x23,
OPC2_32_BO_CMPSWAP_W_POSTINC = 0x03,
OPC2_32_BO_CMPSWAP_W_PREINC = 0x13,
+ OPC2_32_BO_SWAPMSK_W_SHORTOFF = 0x22,
+ OPC2_32_BO_SWAPMSK_W_POSTINC = 0x02,
+ OPC2_32_BO_SWAPMSK_W_PREINC = 0x12,
};
/*OPCM_32_BO_ADDRMODE_LDMST_BITREVERSE_CIRCULAR */
enum {
OPC2_32_BO_SWAP_W_CIRC = 0x10,
OPC2_32_BO_CMPSWAP_W_BR = 0x03,
OPC2_32_BO_CMPSWAP_W_CIRC = 0x13,
+ OPC2_32_BO_SWAPMSK_W_BR = 0x02,
+ OPC2_32_BO_SWAPMSK_W_CIRC = 0x12,
};
/*
* BRC Format