Tighten operand checking of register-shifted-register operands.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137180 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/ARM/ARMInstrInfo.td b/lib/Target/ARM/ARMInstrInfo.td
index e7a6b89..0cbb765 100644 (file)
--- a/lib/Target/ARM/ARMInstrInfo.td
+++ b/lib/Target/ARM/ARMInstrInfo.td
@@ -439,7 +439,7 @@ def so_reg_reg : Operand<i32>,  // reg reg imm
   let PrintMethod = "printSORegRegOperand";
   let DecoderMethod = "DecodeSORegRegOperand";
   let ParserMatchClass = ShiftedRegAsmOperand;
-  let MIOperandInfo = (ops GPR, GPR, i32imm);
+  let MIOperandInfo = (ops GPRnopc, GPRnopc, i32imm);
 }
 
 def ShiftedImmAsmOperand : AsmOperandClass { let Name = "RegShiftedImm"; }
@@ -2541,9 +2541,9 @@ def MOVr_TC : AsI1<0b1101, (outs tcGPR:$Rd), (ins tcGPR:$Rm), DPFrm,
   let Inst{15-12} = Rd;
 }
 
-def MOVsr : AsI1<0b1101, (outs GPR:$Rd), (ins shift_so_reg_reg:$src),
+def MOVsr : AsI1<0b1101, (outs GPRnopc:$Rd), (ins shift_so_reg_reg:$src),
                 DPSoRegRegFrm, IIC_iMOVsr,
-                "mov", "\t$Rd, $src", [(set GPR:$Rd, shift_so_reg_reg:$src)]>,
+                "mov", "\t$Rd, $src", [(set GPRnopc:$Rd, shift_so_reg_reg:$src)]>,
                 UnaryDP {
   bits<4> Rd;
   bits<12> src;

diff --git a/lib/Target/ARM/Disassembler/ARMDisassembler.cpp b/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
index 4e7e582..59bed8d 100644 (file)
--- a/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
+++ b/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
@@ -683,8 +683,8 @@ static bool DecodeSORegRegOperand(llvm::MCInst &Inst, unsigned Val,
   unsigned Rs = fieldFromInstruction32(Val, 8, 4);
 
   // Register-register
-  DecodeGPRRegisterClass(Inst, Rm, Address, Decoder);
-  DecodeGPRRegisterClass(Inst, Rs, Address, Decoder);
+  if (!DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)) return false;
+  if (!DecodeGPRnopcRegisterClass(Inst, Rs, Address, Decoder)) return false;
 
   ARM_AM::ShiftOpc Shift = ARM_AM::lsl;
   switch (type) {

diff --git a/test/MC/Disassembler/ARM/invalid-LSL-regform.txt b/test/MC/Disassembler/ARM/invalid-LSL-regform.txt
index b3a7238..6a1f11f 100644 (file)
--- a/test/MC/Disassembler/ARM/invalid-LSL-regform.txt
+++ b/test/MC/Disassembler/ARM/invalid-LSL-regform.txt
@@ -1,8 +1,7 @@
 # RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& grep {invalid instruction encoding}
-# XFAIL: *
 
 # Opcode=196 Name=MOVs Format=ARM_FORMAT_DPSOREGFRM(5)
-#  31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10  9  8  7  6  5  4  3  2  1  0 
+#  31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10  9  8  7  6  5  4  3  2  1  0
 # -------------------------------------------------------------------------------------------------
 # | 1: 1: 1: 0| 0: 0: 0: 1| 1: 0: 1: 0| 0: 0: 0: 0| 1: 1: 1: 1| 0: 0: 0: 1| 0: 0: 0: 1| 0: 0: 1: 0|
 # -------------------------------------------------------------------------------------------------

diff --git a/test/MC/Disassembler/ARM/invalid-RSC-arm.txt b/test/MC/Disassembler/ARM/invalid-RSC-arm.txt
index b74bcc9..096b909 100644 (file)
--- a/test/MC/Disassembler/ARM/invalid-RSC-arm.txt
+++ b/test/MC/Disassembler/ARM/invalid-RSC-arm.txt
@@ -1,8 +1,7 @@
 # RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& grep {invalid instruction encoding}
-# XFAIL: *
 
 # Opcode=261 Name=RSCrs Format=ARM_FORMAT_DPSOREGFRM(5)
-#  31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10  9  8  7  6  5  4  3  2  1  0 
+#  31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10  9  8  7  6  5  4  3  2  1  0
 # -------------------------------------------------------------------------------------------------
 # | 0: 0: 1: 1| 0: 0: 0: 0| 1: 1: 1: 0| 0: 1: 0: 0| 1: 1: 1: 1| 1: 0: 0: 0| 0: 1: 0: 1| 1: 1: 1: 1|
 # -------------------------------------------------------------------------------------------------