drm/amdgpu: switch to v9_4_3 gfx_funcs callbacks for GC 9.4.3

add gfx_funcs callbacks implemenation based on
gc_v9_4_3 ip headers

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Le Ma <le.ma@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c
index a7246d3..5f85005 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c
@@ -26,6 +26,7 @@
 #include "amdgpu_gfx.h"
 #include "soc15.h"
 #include "soc15_common.h"
+#include "vega10_enum.h"
 
 #include "gc/gc_9_4_3_offset.h"
 #include "gc/gc_9_4_3_sh_mask.h"
@@ -34,6 +35,121 @@
 
 #define RLCG_UCODE_LOADING_START_ADDRESS 0x00002000L
 
+static uint64_t gfx_v9_4_3_get_gpu_clock_counter(struct amdgpu_device *adev)
+{
+       uint64_t clock;
+
+       amdgpu_gfx_off_ctrl(adev, false);
+       mutex_lock(&adev->gfx.gpu_clock_mutex);
+       WREG32_SOC15(GC, 0, regRLC_CAPTURE_GPU_CLOCK_COUNT, 1);
+       clock = (uint64_t)RREG32_SOC15(GC, 0, regRLC_GPU_CLOCK_COUNT_LSB) |
+               ((uint64_t)RREG32_SOC15(GC, 0, regRLC_GPU_CLOCK_COUNT_MSB) << 32ULL);
+       mutex_unlock(&adev->gfx.gpu_clock_mutex);
+       amdgpu_gfx_off_ctrl(adev, true);
+
+       return clock;
+}
+
+static void gfx_v9_4_3_select_se_sh(struct amdgpu_device *adev,
+                                   u32 se_num,
+                                   u32 sh_num,
+                                   u32 instance)
+{
+       u32 data;
+
+       if (instance == 0xffffffff)
+               data = REG_SET_FIELD(0, GRBM_GFX_INDEX,
+                                    INSTANCE_BROADCAST_WRITES, 1);
+       else
+               data = REG_SET_FIELD(0, GRBM_GFX_INDEX,
+                                    INSTANCE_INDEX, instance);
+
+       if (se_num == 0xffffffff)
+               data = REG_SET_FIELD(data, GRBM_GFX_INDEX,
+                                    SE_BROADCAST_WRITES, 1);
+       else
+               data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num);
+
+       if (sh_num == 0xffffffff)
+               data = REG_SET_FIELD(data, GRBM_GFX_INDEX,
+                                    SH_BROADCAST_WRITES, 1);
+       else
+               data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_INDEX, sh_num);
+
+       WREG32_SOC15_RLC_SHADOW_EX(reg, GC, 0, regGRBM_GFX_INDEX, data);
+}
+
+static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t address)
+{
+       WREG32_SOC15_RLC(GC, 0, regSQ_IND_INDEX,
+               (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) |
+               (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) |
+               (address << SQ_IND_INDEX__INDEX__SHIFT) |
+               (SQ_IND_INDEX__FORCE_READ_MASK));
+       return RREG32_SOC15(GC, 0, regSQ_IND_DATA);
+}
+
+static void wave_read_regs(struct amdgpu_device *adev, uint32_t simd,
+                          uint32_t wave, uint32_t thread,
+                          uint32_t regno, uint32_t num, uint32_t *out)
+{
+       WREG32_SOC15_RLC(GC, 0, regSQ_IND_INDEX,
+               (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) |
+               (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) |
+               (regno << SQ_IND_INDEX__INDEX__SHIFT) |
+               (thread << SQ_IND_INDEX__THREAD_ID__SHIFT) |
+               (SQ_IND_INDEX__FORCE_READ_MASK) |
+               (SQ_IND_INDEX__AUTO_INCR_MASK));
+       while (num--)
+               *(out++) = RREG32_SOC15(GC, 0, regSQ_IND_DATA);
+}
+
+static void gfx_v9_4_3_read_wave_data(struct amdgpu_device *adev,
+                                     uint32_t simd, uint32_t wave,
+                                     uint32_t *dst, int *no_fields)
+{
+       /* type 1 wave data */
+       dst[(*no_fields)++] = 1;
+       dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_STATUS);
+       dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_LO);
+       dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_HI);
+       dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_LO);
+       dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_HI);
+       dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_HW_ID);
+       dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_INST_DW0);
+       dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_INST_DW1);
+       dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_GPR_ALLOC);
+       dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_LDS_ALLOC);
+       dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TRAPSTS);
+       dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_IB_STS);
+       dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_IB_DBG0);
+       dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_M0);
+       dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_MODE);
+}
+
+static void gfx_v9_4_3_read_wave_sgprs(struct amdgpu_device *adev, uint32_t simd,
+                                      uint32_t wave, uint32_t start,
+                                      uint32_t size, uint32_t *dst)
+{
+       wave_read_regs(adev, simd, wave, 0,
+                      start + SQIND_WAVE_SGPRS_OFFSET, size, dst);
+}
+
+static void gfx_v9_4_3_read_wave_vgprs(struct amdgpu_device *adev, uint32_t simd,
+                                      uint32_t wave, uint32_t thread,
+                                      uint32_t start, uint32_t size,
+                                      uint32_t *dst)
+{
+       wave_read_regs(adev, simd, wave, thread,
+                      start + SQIND_WAVE_VGPRS_OFFSET, size, dst);
+}
+
+static void gfx_v9_4_3_select_me_pipe_q(struct amdgpu_device *adev,
+                                       u32 me, u32 pipe, u32 q, u32 vm)
+{
+       soc15_grbm_select(adev, me, pipe, q, vm);
+}
+
 static bool gfx_v9_4_3_is_rlc_enabled(struct amdgpu_device *adev)
 {
        uint32_t rlc_setting;
@@ -80,35 +196,6 @@ static int gfx_v9_4_3_rlc_init(struct amdgpu_device *adev)
        return 0;
 }
 
-static void gfx_v9_4_3_select_se_sh(struct amdgpu_device *adev,
-                                   u32 se_num,
-                                   u32 sh_num,
-                                   u32 instance)
-{
-       u32 data;
-
-       if (instance == 0xffffffff)
-               data = REG_SET_FIELD(0, GRBM_GFX_INDEX,
-                                    INSTANCE_BROADCAST_WRITES, 1);
-       else
-               data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_INDEX,
-                                    instance);
-
-       if (se_num == 0xffffffff)
-               data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES,
-                                    1);
-       else
-               data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num);
-
-       if (sh_num == 0xffffffff)
-               data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_BROADCAST_WRITES,
-                                    1);
-       else
-               data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_INDEX, sh_num);
-
-       WREG32_SOC15_RLC_SHADOW_EX(reg, GC, 0, regGRBM_GFX_INDEX, data);
-}
-
 static void gfx_v9_4_3_wait_for_rlc_serdes(struct amdgpu_device *adev)
 {
        u32 i, j, k;
@@ -320,6 +407,15 @@ static bool gfx_v9_4_3_is_rlcg_access_range(struct amdgpu_device *adev, u32 offs
                                        ARRAY_SIZE(rlcg_access_gc_9_4_3));
 }
 
+const struct amdgpu_gfx_funcs gfx_v9_4_3_gfx_funcs = {
+       .get_gpu_clock_counter = &gfx_v9_4_3_get_gpu_clock_counter,
+       .select_se_sh = &gfx_v9_4_3_select_se_sh,
+       .read_wave_data = &gfx_v9_4_3_read_wave_data,
+       .read_wave_sgprs = &gfx_v9_4_3_read_wave_sgprs,
+       .read_wave_vgprs = &gfx_v9_4_3_read_wave_vgprs,
+       .select_me_pipe_q = &gfx_v9_4_3_select_me_pipe_q,
+};
+
 const struct amdgpu_rlc_funcs gfx_v9_4_3_rlc_funcs = {
        .is_rlc_enabled = gfx_v9_4_3_is_rlc_enabled,
        .set_safe_mode = gfx_v9_4_3_set_safe_mode,

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.h b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.h
index d21ea9e..84e6970 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.h
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.h
@@ -24,6 +24,7 @@
 #ifndef __GFX_V9_4_3_H__
 #define __GFX_V9_4_3_H__
 
+extern const struct amdgpu_gfx_funcs gfx_v9_4_3_gfx_funcs;
 extern const struct amdgpu_rlc_funcs gfx_v9_4_3_rlc_funcs;
 
 #endif /* __GFX_V9_4_3_H__ */