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drm/i915: don't write TU size to N1 reg
author
Jesse Barnes
<jbarnes@virtuousgeek.org>
Fri, 10 Sep 2010 18:22:02 +0000
(11:22 -0700)
committer
Chris Wilson
<chris@chris-wilson.co.uk>
Fri, 10 Sep 2010 22:13:48 +0000
(23:13 +0100)
TU size is only part of the M1 and M2 regs, not the N regs. This keeps
us from overwriting a reserved field.
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
drivers/gpu/drm/i915/intel_display.c
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diff --git
a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index
086df96
..
358c301
100644
(file)
--- a/
drivers/gpu/drm/i915/intel_display.c
+++ b/
drivers/gpu/drm/i915/intel_display.c
@@
-4170,7
+4170,7
@@
static int intel_crtc_mode_set(struct drm_crtc *crtc,
if (HAS_PCH_SPLIT(dev)) {
I915_WRITE(data_m1_reg, TU_SIZE(m_n.tu) | m_n.gmch_m);
- I915_WRITE(data_n1_reg,
TU_SIZE(m_n.tu) |
m_n.gmch_n);
+ I915_WRITE(data_n1_reg, m_n.gmch_n);
I915_WRITE(link_m1_reg, m_n.link_m);
I915_WRITE(link_n1_reg, m_n.link_n);