drm/amd/display: add explicit comparator as default optimization check

[why]
memcmp is vulnerable to regression due to dc_clocks structures not being
organized properly (not "current" clock related structures being at the beginning
of the structure) and causes unnecessary setting of the optimize bit

[how]
add a dcn sepcific comparator, implement for dcn2

Signed-off-by: Jun Lei <Jun.Lei@amd.com>
Reviewed-by: Anthony Koo <Anthony.Koo@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c
index 559e169..ecd2cb4 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c
@@ -349,12 +349,36 @@ void dcn2_get_clock(struct clk_mgr *clk_mgr,
        }
 }
 
+static bool dcn2_are_clock_states_equal(struct dc_clocks *a,
+               struct dc_clocks *b)
+{
+       if (a->dispclk_khz != b->dispclk_khz)
+               return false;
+       else if (a->dppclk_khz != b->dppclk_khz)
+               return false;
+       else if (a->dcfclk_khz != b->dcfclk_khz)
+               return false;
+       else if (a->socclk_khz != b->socclk_khz)
+               return false;
+       else if (a->dcfclk_deep_sleep_khz != b->dcfclk_deep_sleep_khz)
+               return false;
+       else if (a->phyclk_khz != b->phyclk_khz)
+               return false;
+       else if (a->dramclk_khz != b->dramclk_khz)
+               return false;
+       else if (a->p_state_change_support != b->p_state_change_support)
+               return false;
+
+       return true;
+}
+
 static struct clk_mgr_funcs dcn2_funcs = {
        .get_dp_ref_clk_frequency = dce12_get_dp_ref_freq_khz,
        .update_clocks = dcn2_update_clocks,
        .init_clocks = dcn2_init_clocks,
        .enable_pme_wa = dcn2_enable_pme_wa,
        .get_clock = dcn2_get_clock,
+       .are_clock_states_equal = dcn2_are_clock_states_equal,
 };
 
 

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c
index a56a989..7ac68e7 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -1681,8 +1681,16 @@ enum surface_update_type dc_check_update_surfaces_for_stream(
                        updates[i].surface->update_flags.raw = 0xFFFFFFFF;
        }
 
-       if (type == UPDATE_TYPE_FAST && memcmp(&dc->current_state->bw_ctx.bw.dcn.clk, &dc->clk_mgr->clks, offsetof(struct dc_clocks, prev_p_state_change_support)) != 0)
-               dc->optimized_required = true;
+       if (type == UPDATE_TYPE_FAST) {
+               // If there's an available clock comparator, we use that.
+               if (dc->clk_mgr->funcs->are_clock_states_equal) {
+                       if (!dc->clk_mgr->funcs->are_clock_states_equal(&dc->clk_mgr->clks, &dc->current_state->bw_ctx.bw.dcn.clk))
+                               dc->optimized_required = true;
+               // Else we fallback to mem compare.
+               } else if (memcmp(&dc->current_state->bw_ctx.bw.dcn.clk, &dc->clk_mgr->clks, offsetof(struct dc_clocks, prev_p_state_change_support)) != 0) {
+                       dc->optimized_required = true;
+               }
+       }
 
        return type;
 }

diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h b/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h
index 76f9ad1..2fdd0ba 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h
@@ -180,6 +180,9 @@ struct clk_mgr_funcs {
                        struct dc_state *context,
                        enum dc_clock_type clock_type,
                        struct dc_clock_config *clock_cfg);
+
+       bool (*are_clock_states_equal) (struct dc_clocks *a,
+                       struct dc_clocks *b);
 };
 
 struct clk_mgr {