clk: mediatek: clk-mt8195-topckgen: Register mfg_ck_fast_ref as generic mux

This clock was being registered as clk-composite through the helpers
for the same in the MediaTek clock APIs but, in reality, this isn't
a composite clock.

Appropriately register this clock with devm_clk_hw_register_mux().
No functional changes.

Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: Chen-Yu Tsai <wenst@chromium.org>
Link: https://lore.kernel.org/r/20220927101128.44758-7-angelogioacchino.delregno@collabora.com
Signed-off-by: Chen-Yu Tsai <wenst@chromium.org>

diff --git a/drivers/clk/mediatek/clk-mt8195-topckgen.c b/drivers/clk/mediatek/clk-mt8195-topckgen.c
index ec70e1f..e1c3ab4 100644 (file)
--- a/drivers/clk/mediatek/clk-mt8195-topckgen.c
+++ b/drivers/clk/mediatek/clk-mt8195-topckgen.c
@@ -1149,11 +1149,6 @@ static const struct mtk_mux top_mtk_muxes[] = {
         */
 };
 
-static struct mtk_composite top_muxes[] = {
-       /* CLK_MISC_CFG_3 */
-       MUX(CLK_TOP_MFG_CK_FAST_REF, "mfg_ck_fast_ref", mfg_fast_parents, 0x0250, 8, 1),
-};
-
 static const struct mtk_composite top_adj_divs[] = {
        DIV_GATE(CLK_TOP_APLL12_DIV0, "apll12_div0", "top_i2si1_mck", 0x0320, 0, 0x0328, 8, 0),
        DIV_GATE(CLK_TOP_APLL12_DIV1, "apll12_div1", "top_i2si2_mck", 0x0320, 1, 0x0328, 8, 8),
@@ -1226,6 +1221,7 @@ static int clk_mt8195_topck_probe(struct platform_device *pdev)
 {
        struct clk_hw_onecell_data *top_clk_data;
        struct device_node *node = pdev->dev.of_node;
+       struct clk_hw *hw;
        int r;
        void __iomem *base;
 
@@ -1253,15 +1249,17 @@ static int clk_mt8195_topck_probe(struct platform_device *pdev)
        if (r)
                goto unregister_factors;
 
-       r = mtk_clk_register_composites(top_muxes, ARRAY_SIZE(top_muxes), base,
-                                       &mt8195_clk_lock, top_clk_data);
-       if (r)
+       hw = devm_clk_hw_register_mux(&pdev->dev, "mfg_ck_fast_ref", mfg_fast_parents,
+                                     ARRAY_SIZE(mfg_fast_parents), CLK_SET_RATE_PARENT,
+                                     (base + 0x250), 8, 1, 0, &mt8195_clk_lock);
+       if (IS_ERR(hw))
                goto unregister_muxes;
+       top_clk_data->hws[CLK_TOP_MFG_CK_FAST_REF] = hw;
 
        r = mtk_clk_register_composites(top_adj_divs, ARRAY_SIZE(top_adj_divs), base,
                                        &mt8195_clk_lock, top_clk_data);
        if (r)
-               goto unregister_composite_muxes;
+               goto unregister_muxes;
 
        r = mtk_clk_register_gates(node, top_clks, ARRAY_SIZE(top_clks), top_clk_data);
        if (r)
@@ -1279,8 +1277,6 @@ unregister_gates:
        mtk_clk_unregister_gates(top_clks, ARRAY_SIZE(top_clks), top_clk_data);
 unregister_composite_divs:
        mtk_clk_unregister_composites(top_adj_divs, ARRAY_SIZE(top_adj_divs), top_clk_data);
-unregister_composite_muxes:
-       mtk_clk_unregister_composites(top_muxes, ARRAY_SIZE(top_muxes), top_clk_data);
 unregister_muxes:
        mtk_clk_unregister_muxes(top_mtk_muxes, ARRAY_SIZE(top_mtk_muxes), top_clk_data);
 unregister_factors:
@@ -1300,7 +1296,6 @@ static int clk_mt8195_topck_remove(struct platform_device *pdev)
        of_clk_del_provider(node);
        mtk_clk_unregister_gates(top_clks, ARRAY_SIZE(top_clks), top_clk_data);
        mtk_clk_unregister_composites(top_adj_divs, ARRAY_SIZE(top_adj_divs), top_clk_data);
-       mtk_clk_unregister_composites(top_muxes, ARRAY_SIZE(top_muxes), top_clk_data);
        mtk_clk_unregister_muxes(top_mtk_muxes, ARRAY_SIZE(top_mtk_muxes), top_clk_data);
        mtk_clk_unregister_factors(top_divs, ARRAY_SIZE(top_divs), top_clk_data);
        mtk_clk_unregister_fixed_clks(top_fixed_clks, ARRAY_SIZE(top_fixed_clks), top_clk_data);