drm/msm/a6xx: Extend and explain UBWC config

Rename lower_bit to hbb_lo and explain what it signifies.
Add explanations (wherever possible to other tunables).

Port setting min_access_length, ubwc_mode and hbb_hi from downstream.

Reviewed-by: Rob Clark <robdclark@gmail.com>
Reviewed-by: Akhil P Oommen <quic_akhilpo@quicinc.com>
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Patchwork: https://patchwork.freedesktop.org/patch/542764/
Signed-off-by: Rob Clark <robdclark@chromium.org>

diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
index 7e0d1df..8aa4670 100644 (file)
--- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
@@ -887,10 +887,25 @@ static void a6xx_set_cp_protect(struct msm_gpu *gpu)
 static void a6xx_set_ubwc_config(struct msm_gpu *gpu)
 {
        struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
-       u32 lower_bit = 2;
-       u32 amsbc = 0;
+       /* Unknown, introduced with A650 family, related to UBWC mode/ver 4 */
        u32 rgb565_predicator = 0;
+       /* Unknown, introduced with A650 family */
        u32 uavflagprd_inv = 0;
+       /* Whether the minimum access length is 64 bits */
+       u32 min_acc_len = 0;
+       /* Entirely magic, per-GPU-gen value */
+       u32 ubwc_mode = 0;
+       /*
+        * The Highest Bank Bit value represents the bit of the highest DDR bank.
+        * We then subtract 13 from it (13 is the minimum value allowed by hw) and
+        * write the lowest two bits of the remaining value as hbb_lo and the
+        * one above it as hbb_hi to the hardware. This should ideally use DRAM
+        * type detection.
+        */
+       u32 hbb_hi = 0;
+       u32 hbb_lo = 2;
+       /* Unknown, introduced with A640/680 */
+       u32 amsbc = 0;
 
        /* a618 is using the hw default values */
        if (adreno_is_a618(adreno_gpu))
@@ -901,32 +916,38 @@ static void a6xx_set_ubwc_config(struct msm_gpu *gpu)
 
        if (adreno_is_a650(adreno_gpu) || adreno_is_a660(adreno_gpu)) {
                /* TODO: get ddr type from bootloader and use 2 for LPDDR4 */
-               lower_bit = 3;
+               hbb_lo = 3;
                amsbc = 1;
                rgb565_predicator = 1;
                uavflagprd_inv = 2;
        }
 
        if (adreno_is_a690(adreno_gpu)) {
-               lower_bit = 2;
+               hbb_lo = 2;
                amsbc = 1;
                rgb565_predicator = 1;
                uavflagprd_inv = 2;
        }
 
        if (adreno_is_7c3(adreno_gpu)) {
-               lower_bit = 1;
+               hbb_lo = 1;
                amsbc = 1;
                rgb565_predicator = 1;
                uavflagprd_inv = 2;
        }
 
        gpu_write(gpu, REG_A6XX_RB_NC_MODE_CNTL,
-               rgb565_predicator << 11 | amsbc << 4 | lower_bit << 1);
-       gpu_write(gpu, REG_A6XX_TPL1_NC_MODE_CNTL, lower_bit << 1);
-       gpu_write(gpu, REG_A6XX_SP_NC_MODE_CNTL,
-               uavflagprd_inv << 4 | lower_bit << 1);
-       gpu_write(gpu, REG_A6XX_UCHE_MODE_CNTL, lower_bit << 21);
+                 rgb565_predicator << 11 | hbb_hi << 10 | amsbc << 4 |
+                 min_acc_len << 3 | hbb_lo << 1 | ubwc_mode);
+
+       gpu_write(gpu, REG_A6XX_TPL1_NC_MODE_CNTL, hbb_hi << 4 |
+                 min_acc_len << 3 | hbb_lo << 1 | ubwc_mode);
+
+       gpu_write(gpu, REG_A6XX_SP_NC_MODE_CNTL, hbb_hi << 10 |
+                 uavflagprd_inv << 4 | min_acc_len << 3 |
+                 hbb_lo << 1 | ubwc_mode);
+
+       gpu_write(gpu, REG_A6XX_UCHE_MODE_CNTL, min_acc_len << 23 | hbb_lo << 21);
 }
 
 static int a6xx_cp_init(struct msm_gpu *gpu)