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dt/bindings: drm/komeda: Add DT bindings for ARM display processor D71
authorjames qian wang (Arm Technology China) <james.qian.wang@arm.com>
Thu, 3 Jan 2019 11:40:04 +0000 (11:40 +0000)
committerLiviu Dudau <Liviu.Dudau@arm.com>
Mon, 14 Jan 2019 11:09:23 +0000 (11:09 +0000)
Add DT bindings documentation for the ARM display processor D71 and later
IPs.

Changes in v4:
- Deleted unnecessary address-cells, size-cells [Liviu Dudau]

Changes in v3:
- Deleted unnecessary property: interrupt-names.
- Dropped 'ports' and moving 'port' up a level.

Signed-off-by: James Qian Wang (Arm Technology China) <james.qian.wang@arm.com>
Reviewed-by: Liviu Dudau <liviu.dudau@arm.com>
Reviewed-by: Rob Herring <robh@kernel.org>
[moved in the same directory as the other Arm display bindings]
Signed-off-by: Liviu Dudau <liviu.dudau@arm.com>
Documentation/devicetree/bindings/display/arm,komeda.txt [new file with mode: 0644]

diff --git a/Documentation/devicetree/bindings/display/arm,komeda.txt b/Documentation/devicetree/bindings/display/arm,komeda.txt
new file mode 100644 (file)
index 0000000..02b2265
--- /dev/null
@@ -0,0 +1,73 @@
+Device Tree bindings for Arm Komeda display driver
+
+Required properties:
+- compatible: Should be "arm,mali-d71"
+- reg: Physical base address and length of the registers in the system
+- interrupts: the interrupt line number of the device in the system
+- clocks: A list of phandle + clock-specifier pairs, one for each entry
+    in 'clock-names'
+- clock-names: A list of clock names. It should contain:
+      - "mclk": for the main processor clock
+      - "pclk": for the APB interface clock
+- #address-cells: Must be 1
+- #size-cells: Must be 0
+
+Required properties for sub-node: pipeline@nq
+Each device contains one or two pipeline sub-nodes (at least one), each
+pipeline node should provide properties:
+- reg: Zero-indexed identifier for the pipeline
+- clocks: A list of phandle + clock-specifier pairs, one for each entry
+    in 'clock-names'
+- clock-names: should contain:
+      - "pxclk": pixel clock
+      - "aclk": AXI interface clock
+
+- port: each pipeline connect to an encoder input port. The connection is
+    modeled using the OF graph bindings specified in
+    Documentation/devicetree/bindings/graph.txt
+
+Optional properties:
+  - memory-region: phandle to a node describing memory (see
+    Documentation/devicetree/bindings/reserved-memory/reserved-memory.txt)
+    to be used for the framebuffer; if not present, the framebuffer may
+    be located anywhere in memory.
+
+Example:
+/ {
+       ...
+
+       dp0: display@c00000 {
+               #address-cells = <1>;
+               #size-cells = <0>;
+               compatible = "arm,mali-d71";
+               reg = <0xc00000 0x20000>;
+               interrupts = <0 168 4>;
+               clocks = <&dpu_mclk>, <&dpu_aclk>;
+               clock-names = "mclk", "pclk";
+
+               dp0_pipe0: pipeline@0 {
+                       clocks = <&fpgaosc2>, <&dpu_aclk>;
+                       clock-names = "pxclk", "aclk";
+                       reg = <0>;
+
+                       port {
+                               dp0_pipe0_out: endpoint {
+                                       remote-endpoint = <&db_dvi0_in>;
+                               };
+                       };
+               };
+
+               dp0_pipe1: pipeline@1 {
+                       clocks = <&fpgaosc2>, <&dpu_aclk>;
+                       clock-names = "pxclk", "aclk";
+                       reg = <1>;
+
+                       port {
+                               dp0_pipe1_out: endpoint {
+                                       remote-endpoint = <&db_dvi1_in>;
+                               };
+                       };
+               };
+       };
+       ...
+};