Under certain circumstances the emulation for the pseries "XICS" interrupt
controller was clearing a pending interrupt from the XISR register, without
also clearing the corresponding priority variable. This will cause
problems later when can trigger sanity checks in the under-development
in-kernel XICS implementation.
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Signed-off-by: Alexander Graf <agraf@suse.de>
if (XISR(ss) && (cppr <= ss->pending_priority)) {
old_xisr = XISR(ss);
ss->xirr &= ~XISR_MASK; /* Clear XISR */
+ ss->pending_priority = 0xff;
qemu_irq_lower(ss->output);
ics_reject(icp->ics, old_xisr);
}
qemu_irq_lower(ss->output);
ss->xirr = ss->pending_priority << 24;
+ ss->pending_priority = 0xff;
trace_xics_icp_accept(xirr, ss->xirr);