help
This enables support for the ARMv8 based Qualcomm chipsets.
+config ARCH_MSMCOBALT
+ bool "Enable Support for Qualcomm MSMCOBALT"
+ depends on ARCH_QCOM
+ help
+ This enables support for the MSMCOBALT chipset. If you do not
+ wish to build a kernel that runs on this chipset, say 'N' here.
+
config ARCH_ROCKCHIP
bool "Rockchip Platforms"
select ARCH_HAS_RESET_CONTROLLER
apq8096-v3-pmi8996-mdm9x55-slimbus-mtp.dtb \
apq8096-v3-pmi8996-dragonboard.dtb
+dtb-$(CONFIG_ARCH_MSMCOBALT) += msmcobalt-sim.dtb \
+ msmcobalt-rumi.dtb \
+ msmcobalt-cdp.dtb \
+ msmcobalt-mtp.dtb \
+ msmcobalt-v2-sim.dtb \
+ msmcobalt-v2-rumi.dtb \
+ msmcobalt-v2-mtp.dtb \
+ msmcobalt-v2-cdp.dtb
+
always := $(dtb-y)
subdir-y := $(dts-dirs)
clean-files := *.dtb
--- /dev/null
+/* Copyright (c) 2015-2016, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <dt-bindings/clock/msm-clocks-cobalt.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+&soc {
+ anoc1_smmu: arm,smmu-anoc1@1680000 {
+ status = "ok";
+ compatible = "qcom,smmu-v2";
+ reg = <0x1680000 0x10000>;
+ #iommu-cells = <1>;
+ qcom,register-save;
+ qcom,skip-init;
+ #global-interrupts = <2>;
+ interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 364 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 365 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 366 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 367 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clock_gcc clk_aggre1_noc_clk>;
+ clock-names = "smmu_aggre1_noc_clk";
+ #clock-cells = <1>;
+ };
+
+ anoc2_smmu: arm,smmu-anoc2@16c0000 {
+ status = "ok";
+ compatible = "qcom,smmu-v2";
+ reg = <0x16c0000 0x40000>;
+ #iommu-cells = <1>;
+ qcom,register-save;
+ qcom,skip-init;
+ #global-interrupts = <2>;
+ interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 463 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clock_gcc clk_aggre2_noc_clk>;
+ clock-names = "smmu_aggre2_noc_clk";
+ #clock-cells = <1>;
+ };
+
+ lpass_q6_smmu: arm,smmu-lpass_q6@5100000 {
+ status = "ok";
+ compatible = "qcom,smmu-v2";
+ reg = <0x5100000 0x4000>;
+ #iommu-cells = <1>;
+ qcom,tz-device-id = "LPASS";
+ qcom,register-save;
+ qcom,skip-init;
+ #global-interrupts = <2>;
+ interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>;
+ vdd-supply = <&gdsc_hlos1_vote_lpass_adsp>;
+ clocks = <&clock_gcc clk_hlos1_vote_lpass_adsp_smmu_clk>;
+ clock-names = "lpass_q6_smmu_clk";
+ #clock-cells = <1>;
+ };
+
+ mmss_smmu: arm,smmu-mmss@cd00000 {
+ status = "ok";
+ compatible = "qcom,smmu-v2";
+ reg = <0xcd00000 0x40000>;
+ #iommu-cells = <1>;
+ qcom,register-save;
+ qcom,skip-init;
+ #global-interrupts = <2>;
+ interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH>;
+ vdd-supply = <&gdsc_bimc_smmu>;
+ clocks = <&clock_mmss clk_mmss_bimc_smmu_ahb_clk>,
+ <&clock_mmss clk_mmss_bimc_smmu_axi_clk>;
+ clock-names = "mmss_smmu_ahb_clk", "mmss_smmu_axi_clk";
+ #clock-cells = <1>;
+ /*
+ * The iommu test framework requires at least one iommu
+ * client to populate debugfs. The presence of a device
+ * "qcom,smmu-v2" alone is not sufficient.
+ */
+ iommus = <&mmss_smmu 1>;
+ };
+
+ kgsl_smmu: arm,smmu-kgsl@5040000 {
+ status = "ok";
+ compatible = "qcom,smmu-v2";
+ reg = <0x5040000 0x10000>;
+ #iommu-cells = <1>;
+ qcom-tz-device-id = "GPU";
+ qcom,dynamic;
+ qcom,register-save;
+ qcom,skip-init;
+ #global-interrupts = <2>;
+ interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
+ vdd-supply = <&gdsc_gpu_cx>;
+ clocks = <&clock_gcc clk_gcc_bimc_gfx_clk>;
+ clock-name = "kgsl_smmu_clk";
+ #clock-cells = <1>;
+ };
+};
--- /dev/null
+/* Copyright (c) 2015, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+&rpm_bus {
+ /* PMCOBALT S1 + S6 = VDD_CX supply */
+ rpm-regulator-smpa1 {
+ compatible = "qcom,rpm-smd-regulator-resource";
+ qcom,resource-name = "rwcx";
+ qcom,resource-id = <0>;
+ qcom,regulator-type = <1>;
+ qcom,hpm-min-load = <100000>;
+ status = "disabled";
+
+ regulator-s1 {
+ compatible = "qcom,rpm-smd-regulator";
+ regulator-name = "pmcobalt_s1";
+ qcom,set = <3>;
+ status = "disabled";
+ };
+ };
+
+ rpm-regulator-smpa2 {
+ compatible = "qcom,rpm-smd-regulator-resource";
+ qcom,resource-name = "smpa";
+ qcom,resource-id = <2>;
+ qcom,regulator-type = <1>;
+ qcom,hpm-min-load = <100000>;
+ status = "disabled";
+
+ regulator-s2 {
+ compatible = "qcom,rpm-smd-regulator";
+ regulator-name = "pmcobalt_s2";
+ qcom,set = <3>;
+ status = "disabled";
+ };
+ };
+
+ rpm-regulator-smpa3 {
+ compatible = "qcom,rpm-smd-regulator-resource";
+ qcom,resource-name = "smpa";
+ qcom,resource-id = <3>;
+ qcom,regulator-type = <1>;
+ qcom,hpm-min-load = <100000>;
+ status = "disabled";
+
+ regulator-s3 {
+ compatible = "qcom,rpm-smd-regulator";
+ regulator-name = "pmcobalt_s3";
+ qcom,set = <3>;
+ status = "disabled";
+ };
+ };
+
+ rpm-regulator-smpa4 {
+ compatible = "qcom,rpm-smd-regulator-resource";
+ qcom,resource-name = "smpa";
+ qcom,resource-id = <4>;
+ qcom,regulator-type = <1>;
+ qcom,hpm-min-load = <100000>;
+ status = "disabled";
+
+ regulator-s4 {
+ compatible = "qcom,rpm-smd-regulator";
+ regulator-name = "pmcobalt_s4";
+ qcom,set = <3>;
+ status = "disabled";
+ };
+ };
+
+ rpm-regulator-smpa5 {
+ compatible = "qcom,rpm-smd-regulator-resource";
+ qcom,resource-name = "smpa";
+ qcom,resource-id = <5>;
+ qcom,regulator-type = <1>;
+ qcom,hpm-min-load = <100000>;
+ status = "disabled";
+
+ regulator-s5 {
+ compatible = "qcom,rpm-smd-regulator";
+ regulator-name = "pmcobalt_s5";
+ qcom,set = <3>;
+ status = "disabled";
+ };
+ };
+
+ rpm-regulator-smpa7 {
+ compatible = "qcom,rpm-smd-regulator-resource";
+ qcom,resource-name = "smpa";
+ qcom,resource-id = <7>;
+ qcom,regulator-type = <1>;
+ qcom,hpm-min-load = <100000>;
+ status = "disabled";
+
+ regulator-s7 {
+ compatible = "qcom,rpm-smd-regulator";
+ regulator-name = "pmcobalt_s7";
+ qcom,set = <3>;
+ status = "disabled";
+ };
+ };
+
+ rpm-regulator-smpa8 {
+ compatible = "qcom,rpm-smd-regulator-resource";
+ qcom,resource-name = "smpa";
+ qcom,resource-id = <8>;
+ qcom,regulator-type = <1>;
+ qcom,hpm-min-load = <100000>;
+ status = "disabled";
+
+ regulator-s8 {
+ compatible = "qcom,rpm-smd-regulator";
+ regulator-name = "pmcobalt_s8";
+ qcom,set = <3>;
+ status = "disabled";
+ };
+ };
+
+ /* PMCOBALT S9 = VDD_MX supply */
+ rpm-regulator-smpa9 {
+ compatible = "qcom,rpm-smd-regulator-resource";
+ qcom,resource-name = "rwmx";
+ qcom,resource-id = <0>;
+ qcom,regulator-type = <1>;
+ qcom,hpm-min-load = <100000>;
+ status = "disabled";
+
+ regulator-s9 {
+ compatible = "qcom,rpm-smd-regulator";
+ regulator-name = "pmcobalt_s9";
+ qcom,set = <3>;
+ status = "disabled";
+ };
+ };
+
+ rpm-regulator-ldoa1 {
+ compatible = "qcom,rpm-smd-regulator-resource";
+ qcom,resource-name = "ldoa";
+ qcom,resource-id = <1>;
+ qcom,regulator-type = <0>;
+ qcom,hpm-min-load = <10000>;
+ status = "disabled";
+
+ regulator-l1 {
+ compatible = "qcom,rpm-smd-regulator";
+ regulator-name = "pmcobalt_l1";
+ qcom,set = <3>;
+ status = "disabled";
+ };
+ };
+
+ rpm-regulator-ldoa2 {
+ compatible = "qcom,rpm-smd-regulator-resource";
+ qcom,resource-name = "ldoa";
+ qcom,resource-id = <2>;
+ qcom,regulator-type = <0>;
+ qcom,hpm-min-load = <10000>;
+ status = "disabled";
+
+ regulator-l2 {
+ compatible = "qcom,rpm-smd-regulator";
+ regulator-name = "pmcobalt_l2";
+ qcom,set = <3>;
+ status = "disabled";
+ };
+ };
+
+ rpm-regulator-ldoa3 {
+ compatible = "qcom,rpm-smd-regulator-resource";
+ qcom,resource-name = "ldoa";
+ qcom,resource-id = <3>;
+ qcom,regulator-type = <0>;
+ qcom,hpm-min-load = <10000>;
+ status = "disabled";
+
+ regulator-l3 {
+ compatible = "qcom,rpm-smd-regulator";
+ regulator-name = "pmcobalt_l3";
+ qcom,set = <3>;
+ status = "disabled";
+ };
+ };
+
+ rpm-regulator-ldoa4 {
+ compatible = "qcom,rpm-smd-regulator-resource";
+ qcom,resource-name = "ldoa";
+ qcom,resource-id = <4>;
+ qcom,regulator-type = <0>;
+ qcom,hpm-min-load = <10000>;
+ status = "disabled";
+
+ regulator-l4 {
+ compatible = "qcom,rpm-smd-regulator";
+ regulator-name = "pmcobalt_l4";
+ qcom,set = <3>;
+ status = "disabled";
+ };
+ };
+
+ rpm-regulator-ldoa6 {
+ compatible = "qcom,rpm-smd-regulator-resource";
+ qcom,resource-name = "ldoa";
+ qcom,resource-id = <6>;
+ qcom,regulator-type = <0>;
+ qcom,hpm-min-load = <10000>;
+ status = "disabled";
+
+ regulator-l6 {
+ compatible = "qcom,rpm-smd-regulator";
+ regulator-name = "pmcobalt_l6";
+ qcom,set = <3>;
+ status = "disabled";
+ };
+ };
+
+ rpm-regulator-ldoa8 {
+ compatible = "qcom,rpm-smd-regulator-resource";
+ qcom,resource-name = "ldoa";
+ qcom,resource-id = <8>;
+ qcom,regulator-type = <0>;
+ qcom,hpm-min-load = <10000>;
+ status = "disabled";
+
+ regulator-l8 {
+ compatible = "qcom,rpm-smd-regulator";
+ regulator-name = "pmcobalt_l8";
+ qcom,set = <3>;
+ status = "disabled";
+ };
+ };
+
+ rpm-regulator-ldoa9 {
+ compatible = "qcom,rpm-smd-regulator-resource";
+ qcom,resource-name = "ldoa";
+ qcom,resource-id = <9>;
+ qcom,regulator-type = <0>;
+ qcom,hpm-min-load = <10000>;
+ status = "disabled";
+
+ regulator-l9 {
+ compatible = "qcom,rpm-smd-regulator";
+ regulator-name = "pmcobalt_l9";
+ qcom,set = <3>;
+ status = "disabled";
+ };
+ };
+
+ rpm-regulator-ldoa10 {
+ compatible = "qcom,rpm-smd-regulator-resource";
+ qcom,resource-name = "ldoa";
+ qcom,resource-id = <10>;
+ qcom,regulator-type = <0>;
+ qcom,hpm-min-load = <10000>;
+ status = "disabled";
+
+ regulator-l10 {
+ compatible = "qcom,rpm-smd-regulator";
+ regulator-name = "pmcobalt_l10";
+ qcom,set = <3>;
+ status = "disabled";
+ };
+ };
+
+ rpm-regulator-ldoa11 {
+ compatible = "qcom,rpm-smd-regulator-resource";
+ qcom,resource-name = "ldoa";
+ qcom,resource-id = <11>;
+ qcom,regulator-type = <0>;
+ qcom,hpm-min-load = <10000>;
+ status = "disabled";
+
+ regulator-l11 {
+ compatible = "qcom,rpm-smd-regulator";
+ regulator-name = "pmcobalt_l11";
+ qcom,set = <3>;
+ status = "disabled";
+ };
+ };
+
+ rpm-regulator-ldoa12 {
+ compatible = "qcom,rpm-smd-regulator-resource";
+ qcom,resource-name = "ldoa";
+ qcom,resource-id = <12>;
+ qcom,regulator-type = <0>;
+ qcom,hpm-min-load = <10000>;
+ status = "disabled";
+
+ regulator-l12 {
+ compatible = "qcom,rpm-smd-regulator";
+ regulator-name = "pmcobalt_l12";
+ qcom,set = <3>;
+ status = "disabled";
+ };
+ };
+
+ rpm-regulator-ldoa13 {
+ compatible = "qcom,rpm-smd-regulator-resource";
+ qcom,resource-name = "ldoa";
+ qcom,resource-id = <13>;
+ qcom,regulator-type = <0>;
+ qcom,hpm-min-load = <10000>;
+ status = "disabled";
+
+ regulator-l13 {
+ compatible = "qcom,rpm-smd-regulator";
+ regulator-name = "pmcobalt_l13";
+ qcom,set = <3>;
+ status = "disabled";
+ };
+ };
+
+ rpm-regulator-ldoa14 {
+ compatible = "qcom,rpm-smd-regulator-resource";
+ qcom,resource-name = "ldoa";
+ qcom,resource-id = <14>;
+ qcom,regulator-type = <0>;
+ qcom,hpm-min-load = <10000>;
+ status = "disabled";
+
+ regulator-l14 {
+ compatible = "qcom,rpm-smd-regulator";
+ regulator-name = "pmcobalt_l14";
+ qcom,set = <3>;
+ status = "disabled";
+ };
+ };
+
+ rpm-regulator-ldoa15 {
+ compatible = "qcom,rpm-smd-regulator-resource";
+ qcom,resource-name = "ldoa";
+ qcom,resource-id = <15>;
+ qcom,regulator-type = <0>;
+ qcom,hpm-min-load = <10000>;
+ status = "disabled";
+
+ regulator-l15 {
+ compatible = "qcom,rpm-smd-regulator";
+ regulator-name = "pmcobalt_l15";
+ qcom,set = <3>;
+ status = "disabled";
+ };
+ };
+
+ rpm-regulator-ldoa16 {
+ compatible = "qcom,rpm-smd-regulator-resource";
+ qcom,resource-name = "ldoa";
+ qcom,resource-id = <16>;
+ qcom,regulator-type = <0>;
+ qcom,hpm-min-load = <10000>;
+ status = "disabled";
+
+ regulator-l16 {
+ compatible = "qcom,rpm-smd-regulator";
+ regulator-name = "pmcobalt_l16";
+ qcom,set = <3>;
+ status = "disabled";
+ };
+ };
+
+ rpm-regulator-ldoa17 {
+ compatible = "qcom,rpm-smd-regulator-resource";
+ qcom,resource-name = "ldoa";
+ qcom,resource-id = <17>;
+ qcom,regulator-type = <0>;
+ qcom,hpm-min-load = <10000>;
+ status = "disabled";
+
+ regulator-l17 {
+ compatible = "qcom,rpm-smd-regulator";
+ regulator-name = "pmcobalt_l17";
+ qcom,set = <3>;
+ status = "disabled";
+ };
+ };
+
+ rpm-regulator-ldoa18 {
+ compatible = "qcom,rpm-smd-regulator-resource";
+ qcom,resource-name = "ldoa";
+ qcom,resource-id = <18>;
+ qcom,regulator-type = <0>;
+ qcom,hpm-min-load = <10000>;
+ status = "disabled";
+
+ regulator-l18 {
+ compatible = "qcom,rpm-smd-regulator";
+ regulator-name = "pmcobalt_l18";
+ qcom,set = <3>;
+ status = "disabled";
+ };
+ };
+
+ rpm-regulator-ldoa19 {
+ compatible = "qcom,rpm-smd-regulator-resource";
+ qcom,resource-name = "ldoa";
+ qcom,resource-id = <19>;
+ qcom,regulator-type = <0>;
+ qcom,hpm-min-load = <10000>;
+ status = "disabled";
+
+ regulator-l19 {
+ compatible = "qcom,rpm-smd-regulator";
+ regulator-name = "pmcobalt_l19";
+ qcom,set = <3>;
+ status = "disabled";
+ };
+ };
+
+ rpm-regulator-ldoa20 {
+ compatible = "qcom,rpm-smd-regulator-resource";
+ qcom,resource-name = "ldoa";
+ qcom,resource-id = <20>;
+ qcom,regulator-type = <0>;
+ qcom,hpm-min-load = <10000>;
+ status = "disabled";
+
+ regulator-l20 {
+ compatible = "qcom,rpm-smd-regulator";
+ regulator-name = "pmcobalt_l20";
+ qcom,set = <3>;
+ status = "disabled";
+ };
+ };
+
+ rpm-regulator-ldoa21 {
+ compatible = "qcom,rpm-smd-regulator-resource";
+ qcom,resource-name = "ldoa";
+ qcom,resource-id = <21>;
+ qcom,regulator-type = <0>;
+ qcom,hpm-min-load = <10000>;
+ status = "disabled";
+
+ regulator-l21 {
+ compatible = "qcom,rpm-smd-regulator";
+ regulator-name = "pmcobalt_l21";
+ qcom,set = <3>;
+ status = "disabled";
+ };
+ };
+
+ rpm-regulator-ldoa22 {
+ compatible = "qcom,rpm-smd-regulator-resource";
+ qcom,resource-name = "ldoa";
+ qcom,resource-id = <22>;
+ qcom,regulator-type = <0>;
+ qcom,hpm-min-load = <10000>;
+ status = "disabled";
+
+ regulator-l22 {
+ compatible = "qcom,rpm-smd-regulator";
+ regulator-name = "pmcobalt_l22";
+ qcom,set = <3>;
+ status = "disabled";
+ };
+ };
+
+ rpm-regulator-ldoa23 {
+ compatible = "qcom,rpm-smd-regulator-resource";
+ qcom,resource-name = "ldoa";
+ qcom,resource-id = <23>;
+ qcom,regulator-type = <0>;
+ qcom,hpm-min-load = <10000>;
+ status = "disabled";
+
+ regulator-l23 {
+ compatible = "qcom,rpm-smd-regulator";
+ regulator-name = "pmcobalt_l23";
+ qcom,set = <3>;
+ status = "disabled";
+ };
+ };
+
+ rpm-regulator-ldoa24 {
+ compatible = "qcom,rpm-smd-regulator-resource";
+ qcom,resource-name = "ldoa";
+ qcom,resource-id = <24>;
+ qcom,regulator-type = <0>;
+ qcom,hpm-min-load = <10000>;
+ status = "disabled";
+
+ regulator-l24 {
+ compatible = "qcom,rpm-smd-regulator";
+ regulator-name = "pmcobalt_l24";
+ qcom,set = <3>;
+ status = "disabled";
+ };
+ };
+
+ rpm-regulator-ldoa25 {
+ compatible = "qcom,rpm-smd-regulator-resource";
+ qcom,resource-name = "ldoa";
+ qcom,resource-id = <25>;
+ qcom,regulator-type = <0>;
+ qcom,hpm-min-load = <10000>;
+ status = "disabled";
+
+ regulator-l25 {
+ compatible = "qcom,rpm-smd-regulator";
+ regulator-name = "pmcobalt_l25";
+ qcom,set = <3>;
+ status = "disabled";
+ };
+ };
+
+ rpm-regulator-ldoa26 {
+ compatible = "qcom,rpm-smd-regulator-resource";
+ qcom,resource-name = "ldoa";
+ qcom,resource-id = <26>;
+ qcom,regulator-type = <0>;
+ qcom,hpm-min-load = <10000>;
+ status = "disabled";
+
+ regulator-l26 {
+ compatible = "qcom,rpm-smd-regulator";
+ regulator-name = "pmcobalt_l26";
+ qcom,set = <3>;
+ status = "disabled";
+ };
+ };
+
+ rpm-regulator-ldoa27 {
+ compatible = "qcom,rpm-smd-regulator-resource";
+ qcom,resource-name = "ldoa";
+ qcom,resource-id = <27>;
+ qcom,regulator-type = <0>;
+ qcom,hpm-min-load = <10000>;
+ status = "disabled";
+
+ regulator-l27 {
+ compatible = "qcom,rpm-smd-regulator";
+ regulator-name = "pmcobalt_l27";
+ qcom,set = <3>;
+ status = "disabled";
+ };
+ };
+
+ rpm-regulator-ldoa28 {
+ compatible = "qcom,rpm-smd-regulator-resource";
+ qcom,resource-name = "ldoa";
+ qcom,resource-id = <28>;
+ qcom,regulator-type = <0>;
+ qcom,hpm-min-load = <10000>;
+ status = "disabled";
+
+ regulator-l28 {
+ compatible = "qcom,rpm-smd-regulator";
+ regulator-name = "pmcobalt_l28";
+ qcom,set = <3>;
+ status = "disabled";
+ };
+ };
+
+ rpm-regulator-vsa1 {
+ compatible = "qcom,rpm-smd-regulator-resource";
+ qcom,resource-name = "vsa";
+ qcom,resource-id = <1>;
+ qcom,regulator-type = <2>;
+ status = "disabled";
+
+ regulator-lvs1 {
+ compatible = "qcom,rpm-smd-regulator";
+ regulator-name = "pmcobalt_lvs1";
+ qcom,set = <3>;
+ status = "disabled";
+ };
+ };
+
+ rpm-regulator-vsa2 {
+ compatible = "qcom,rpm-smd-regulator-resource";
+ qcom,resource-name = "vsa";
+ qcom,resource-id = <2>;
+ qcom,regulator-type = <2>;
+ status = "disabled";
+
+ regulator-lvs2 {
+ compatible = "qcom,rpm-smd-regulator";
+ regulator-name = "pmcobalt_lvs2";
+ qcom,set = <3>;
+ status = "disabled";
+ };
+ };
+
+ rpm-regulator-bobb {
+ compatible = "qcom,rpm-smd-regulator-resource";
+ qcom,resource-name = "bobb";
+ qcom,resource-id = <1>;
+ qcom,regulator-type = <4>;
+ status = "disabled";
+
+ regulator-bob {
+ compatible = "qcom,rpm-smd-regulator";
+ regulator-name = "pmcobalt_bob";
+ qcom,set = <3>;
+ status = "disabled";
+ };
+ };
+};
--- /dev/null
+/* Copyright (c) 2016, The Linux Foundation. All rights reserved.
+ *
+ * This program is Mree software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <dt-bindings/msm/msm-bus-ids.h>
+
+&soc {
+ ad_hoc_bus: ad-hoc-bus {
+ /*Version = 4 */
+ compatible = "qcom,msm-bus-device";
+ reg = <0x1620000 0x40000>,
+ <0x1000000 0x80000>,
+ <0x1500000 0x10000>,
+ <0x1660000 0x60000>,
+ <0x1700000 0x60000>,
+ <0x17900000 0x10000>,
+ <0x1740000 0x10000>;
+
+ reg-names = "snoc-base", "bimc-base", "cnoc-base",
+ "a1noc-base", "a2noc-base", "gnoc-base",
+ "mnoc-base";
+
+ /*Buses*/
+ fab_a1noc: fab-a1noc {
+ cell-id = <MSM_BUS_FAB_A1_NOC>;
+ label = "fab-a1noc";
+ qcom,fab-dev;
+ qcom,base-name = "a1noc-base";
+ qcom,bypass-qos-prg;
+ qcom,bus-type = <1>;
+ qcom,qos-off = <4096>;
+ qcom,base-offset = <36864>;
+ clock-names = "bus_clk", "bus_a_clk";
+ clocks = <&clock_gcc clk_aggre1_noc_clk>,
+ <&clock_gcc clk_aggre1_noc_a_clk>;
+ };
+
+ fab_a2noc: fab-a2noc {
+ cell-id = <MSM_BUS_FAB_A2_NOC>;
+ label = "fab-a2noc";
+ qcom,fab-dev;
+ qcom,base-name = "a2noc-base";
+ qcom,bypass-qos-prg;
+ qcom,bus-type = <1>;
+ qcom,qos-off = <4096>;
+ qcom,base-offset = <20480>;
+ clock-names = "bus_clk", "bus_a_clk";
+ clocks = <&clock_gcc clk_aggre2_noc_clk>,
+ <&clock_gcc clk_aggre2_noc_a_clk>;
+ };
+
+ fab_bimc: fab-bimc {
+ cell-id = <MSM_BUS_FAB_BIMC>;
+ label = "fab-bimc";
+ qcom,fab-dev;
+ qcom,base-name = "bimc-base";
+ qcom,bus-type = <2>;
+ qcom,bypass-qos-prg;
+ qcom,util-fact = <153>;
+ clock-names = "bus_clk", "bus_a_clk";
+ clocks = <&clock_gcc clk_bimc_clk>,
+ <&clock_gcc clk_bimc_a_clk>;
+ };
+
+ fab_cnoc: fab-cnoc {
+ cell-id = <MSM_BUS_FAB_CONFIG_NOC>;
+ label = "fab-cnoc";
+ qcom,fab-dev;
+ qcom,base-name = "cnoc-base";
+ qcom,bypass-qos-prg;
+ qcom,bus-type = <1>;
+ clock-names = "bus_clk", "bus_a_clk";
+ clocks = <&clock_gcc clk_cnoc_clk>,
+ <&clock_gcc clk_cnoc_a_clk>;
+ };
+
+ fab_cr_virt: fab-cr_virt {
+ cell-id = <MSM_BUS_FAB_CR_VIRT>;
+ label = "fab-cr_virt";
+ qcom,virt-dev;
+ qcom,base-name = "cr_virt-base";
+ qcom,bypass-qos-prg;
+ };
+
+ fab_gnoc: fab-gnoc {
+ cell-id = <MSM_BUS_FAB_GNOC>;
+ label = "fab-gnoc";
+ qcom,fab-dev;
+ qcom,virt-dev;
+ qcom,base-name = "gnoc-base";
+ qcom,bypass-qos-prg;
+ clock-names = "bus_clk", "bus_a_clk";
+ clocks = <&clock_gcc clk_bimc_clk>,
+ <&clock_gcc clk_bimc_a_clk>;
+ };
+
+ fab_mnoc: fab-mnoc {
+ cell-id = <MSM_BUS_FAB_MMSS_NOC>;
+ label = "fab-mnoc";
+ qcom,fab-dev;
+ qcom,base-name = "mnoc-base";
+ qcom,bypass-qos-prg;
+ qcom,bus-type = <1>;
+ qcom,qos-off = <4096>;
+ qcom,base-offset = <16384>;
+ qcom,util-fact = <153>;
+ clock-names = "bus_clk", "bus_a_clk";
+ clocks = <&clock_gcc clk_mmssnoc_axi_clk>,
+ <&clock_gcc clk_mmssnoc_axi_a_clk>;
+ };
+
+ fab_snoc: fab-snoc {
+ cell-id = <MSM_BUS_FAB_SYS_NOC>;
+ label = "fab-snoc";
+ qcom,fab-dev;
+ qcom,base-name = "snoc-base";
+ qcom,bypass-qos-prg;
+ qcom,bus-type = <1>;
+ qcom,qos-off = <4096>;
+ qcom,base-offset = <20480>;
+ clock-names = "bus_clk", "bus_a_clk";
+ clocks = <&clock_gcc clk_snoc_clk>,
+ <&clock_gcc clk_snoc_a_clk>;
+ };
+
+ /*Masters*/
+
+ mas_pcie_0: mas-pcie-0 {
+ cell-id = <MSM_BUS_MASTER_PCIE>;
+ label = "mas-pcie-0";
+ qcom,buswidth = <16>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,qport = <1>;
+ qcom,qos-mode = "fixed";
+ qcom,connections = <&slv_a1noc_snoc>;
+ qcom,prio1 = <1>;
+ qcom,prio0 = <1>;
+ qcom,bus-dev = <&fab_a1noc>;
+ qcom,mas-rpm-id = <ICBID_MASTER_PCIE_0>;
+ };
+
+ mas_usb3: mas-usb3 {
+ cell-id = <MSM_BUS_MASTER_USB3>;
+ label = "mas-usb3";
+ qcom,buswidth = <16>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,qport = <3>;
+ qcom,qos-mode = "fixed";
+ qcom,connections = <&slv_a1noc_snoc>;
+ qcom,prio1 = <1>;
+ qcom,prio0 = <1>;
+ qcom,bus-dev = <&fab_a1noc>;
+ qcom,mas-rpm-id = <ICBID_MASTER_USB3>;
+ };
+
+ mas_ufs: mas-ufs {
+ cell-id = <MSM_BUS_MASTER_UFS>;
+ label = "mas-ufs";
+ qcom,buswidth = <16>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,qport = <0>;
+ qcom,qos-mode = "fixed";
+ qcom,connections = <&slv_a1noc_snoc>;
+ qcom,prio1 = <1>;
+ qcom,prio0 = <1>;
+ qcom,bus-dev = <&fab_a1noc>;
+ qcom,mas-rpm-id = <ICBID_MASTER_UFS>;
+ };
+
+ mas_blsp_2: mas-blsp-2 {
+ cell-id = <MSM_BUS_MASTER_BLSP_2>;
+ label = "mas-blsp-2";
+ qcom,buswidth = <16>;
+ qcom,agg-ports = <1>;
+ qcom,qport = <3>;
+ qcom,qos-mode = "fixed";
+ qcom,connections = <&slv_a1noc_snoc>;
+ qcom,bus-dev = <&fab_a1noc>;
+ qcom,mas-rpm-id = <ICBID_MASTER_BLSP_2>;
+ };
+
+ mas_cnoc_a2noc: mas-cnoc-a2noc {
+ cell-id = <0>;
+ label = "mas-cnoc-a2noc";
+ qcom,buswidth = <8>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,connections = <&slv_a2noc_snoc>;
+ qcom,bus-dev = <&fab_a2noc>;
+ qcom,mas-rpm-id = <ICBID_MASTER_CNOC_A2NOC>;
+ };
+
+ mas_ipa: mas-ipa {
+ cell-id = <MSM_BUS_MASTER_IPA>;
+ label = "mas-ipa";
+ qcom,buswidth = <8>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,qport = <1>;
+ qcom,qos-mode = "fixed";
+ qcom,connections = <&slv_a2noc_snoc>;
+ qcom,prio1 = <1>;
+ qcom,prio0 = <1>;
+ qcom,bus-dev = <&fab_a2noc>;
+ qcom,mas-rpm-id = <ICBID_MASTER_IPA>;
+ };
+
+ mas_sdcc_2: mas-sdcc-2 {
+ cell-id = <MSM_BUS_MASTER_SDCC_2>;
+ label = "mas-sdcc-2";
+ qcom,buswidth = <8>;
+ qcom,agg-ports = <1>;
+ qcom,qport = <6>;
+ qcom,qos-mode = "fixed";
+ qcom,connections = <&slv_a2noc_snoc>;
+ qcom,bus-dev = <&fab_a2noc>;
+ qcom,mas-rpm-id = <ICBID_MASTER_SDCC_2>;
+ };
+
+ mas_sdcc_4: mas-sdcc-4 {
+ cell-id = <MSM_BUS_MASTER_SDCC_4>;
+ label = "mas-sdcc-4";
+ qcom,buswidth = <8>;
+ qcom,agg-ports = <1>;
+ qcom,qport = <7>;
+ qcom,qos-mode = "fixed";
+ qcom,connections = <&slv_a2noc_snoc>;
+ qcom,bus-dev = <&fab_a2noc>;
+ qcom,mas-rpm-id = <ICBID_MASTER_SDCC_4>;
+ };
+
+ mas_tsif: mas-tsif {
+ cell-id = <MSM_BUS_MASTER_TSIF>;
+ label = "mas-tsif";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,connections = <&slv_a2noc_snoc>;
+ qcom,bus-dev = <&fab_a2noc>;
+ qcom,mas-rpm-id = <ICBID_MASTER_TSIF>;
+ };
+
+ mas_blsp_1: mas-blsp-1 {
+ cell-id = <MSM_BUS_MASTER_BLSP_1>;
+ label = "mas-blsp-1";
+ qcom,buswidth = <16>;
+ qcom,agg-ports = <1>;
+ qcom,qport = <8>;
+ qcom,qos-mode = "fixed";
+ qcom,connections = <&slv_a2noc_snoc>;
+ qcom,bus-dev = <&fab_a2noc>;
+ qcom,mas-rpm-id = <ICBID_MASTER_BLSP_1>;
+ };
+
+ mas_cr_virt_a2noc: mas-cr-virt-a2noc {
+ cell-id = <MSM_BUS_MASTER_CRVIRT_A2NOC>;
+ label = "mas-cr-virt-a2noc";
+ qcom,buswidth = <8>;
+ qcom,agg-ports = <1>;
+ qcom,qport = <9>;
+ qcom,qos-mode = "fixed";
+ qcom,connections = <&slv_a2noc_snoc>;
+ qcom,bus-dev = <&fab_a2noc>;
+ qcom,mas-rpm-id = <ICBID_MASTER_CRVIRT_A2NOC>;
+ };
+
+ mas_gnoc_bimc: mas-gnoc-bimc {
+ cell-id = <MSM_BUS_MASTER_GNOC_BIMC>;
+ label = "mas-gnoc-bimc";
+ qcom,buswidth = <8>;
+ qcom,agg-ports = <2>;
+ qcom,ap-owned;
+ qcom,qport = <0>;
+ qcom,qos-mode = "fixed";
+ qcom,connections = <&slv_ebi &slv_bimc_snoc_0>;
+ qcom,prio-lvl = <0>;
+ qcom,prio-rd = <0>;
+ qcom,prio-wr = <0>;
+ qcom,bus-dev = <&fab_bimc>;
+ qcom,mas-rpm-id = <ICBID_MASTER_GNOC_BIMC>;
+ };
+
+ mas_oxili: mas-oxili {
+ cell-id = <MSM_BUS_MASTER_GRAPHICS_3D>;
+ label = "mas-oxili";
+ qcom,buswidth = <8>;
+ qcom,agg-ports = <2>;
+ qcom,ap-owned;
+ qcom,qport = <1>;
+ qcom,qos-mode = "bypass";
+ qcom,connections = < &slv_bimc_snoc_1
+ &slv_hmss_l3&slv_ebi &slv_bimc_snoc_0>;
+ qcom,bus-dev = <&fab_bimc>;
+ qcom,mas-rpm-id = <ICBID_MASTER_GFX3D>;
+ };
+
+ mas_mnoc_bimc: mas-mnoc-bimc {
+ cell-id = <MSM_BUS_MNOC_BIMC_MAS>;
+ label = "mas-mnoc-bimc";
+ qcom,buswidth = <8>;
+ qcom,agg-ports = <2>;
+ qcom,ap-owned;
+ qcom,qport = <2>;
+ qcom,qos-mode = "bypass";
+ qcom,connections = < &slv_bimc_snoc_1
+ &slv_hmss_l3&slv_ebi &slv_bimc_snoc_0>;
+ qcom,bus-dev = <&fab_bimc>;
+ qcom,mas-rpm-id = <ICBID_MASTER_MNOC_BIMC>;
+ };
+
+ mas_snoc_bimc: mas-snoc-bimc {
+ cell-id = <MSM_BUS_SNOC_BIMC_MAS>;
+ label = "mas-snoc-bimc";
+ qcom,buswidth = <8>;
+ qcom,agg-ports = <2>;
+ qcom,qport = <3>;
+ qcom,qos-mode = "bypass";
+ qcom,connections = < &slv_hmss_l3&slv_ebi>;
+ qcom,bus-dev = <&fab_bimc>;
+ qcom,mas-rpm-id = <ICBID_MASTER_SNOC_BIMC>;
+ };
+
+ mas_snoc_cnoc: mas-snoc-cnoc {
+ cell-id = <MSM_BUS_SNOC_CNOC_MAS>;
+ label = "mas-snoc-cnoc";
+ qcom,buswidth = <8>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,connections = < &slv_skl &slv_blsp_2
+ &slv_message_ram
+ &slv_tlmm_west &slv_tsif
+ &slv_mpm &slv_bimc_cfg
+ &slv_tlmm_east &slv_spdm
+ &slv_pimem_cfg &slv_a1noc_smmu_cfg
+ &slv_blsp_1 &slv_clk_ctl
+ &slv_prng &slv_usb3_0
+ &slv_qdss_cfg &slv_qm_cfg
+ &slv_a2noc_cfg &slv_pmic_arb
+ &slv_ufs_cfg &slv_srvc_cnoc
+ &slv_ahb2phy &slv_ipa
+ &slv_glm &slv_snoc_cfg
+ &slv_ssc_cfg &slv_sdcc_2
+ &slv_sdcc_4 &slv_pdm
+ &slv_cnoc_mnoc_mmss_cfg &slv_cnoc_mnoc_cfg
+ &slv_mss_cfg &slv_imem_cfg
+ &slv_a1noc_cfg &slv_gpuss_cfg
+ &slv_tcsr &slv_tlmm_north>;
+ qcom,bus-dev = <&fab_cnoc>;
+ qcom,mas-rpm-id = <ICBID_MASTER_SNOC_CNOC>;
+ };
+
+ mas_qdss_dap: mas-qdss-dap {
+ cell-id = <MSM_BUS_MASTER_QDSS_DAP>;
+ label = "mas-qdss-dap";
+ qcom,buswidth = <8>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,connections = < &slv_skl &slv_blsp_2
+ &slv_message_ram
+ &slv_tlmm_west &slv_tsif
+ &slv_mpm &slv_bimc_cfg
+ &slv_tlmm_east &slv_spdm
+ &slv_pimem_cfg &slv_a1noc_smmu_cfg
+ &slv_blsp_1 &slv_clk_ctl
+ &slv_prng &slv_usb3_0
+ &slv_qdss_cfg &slv_qm_cfg
+ &slv_a2noc_cfg &slv_pmic_arb
+ &slv_ufs_cfg &slv_srvc_cnoc
+ &slv_ahb2phy &slv_ipa
+ &slv_glm &slv_snoc_cfg
+ &slv_sdcc_2 &slv_sdcc_4
+ &slv_pdm &slv_cnoc_mnoc_mmss_cfg
+ &slv_cnoc_mnoc_cfg &slv_mss_cfg
+ &slv_imem_cfg &slv_a1noc_cfg
+ &slv_gpuss_cfg &slv_ssc_cfg
+ &slv_tcsr &slv_tlmm_north
+ &slv_cnoc_a2noc>;
+ qcom,bus-dev = <&fab_cnoc>;
+ qcom,mas-rpm-id = <ICBID_MASTER_QDSS_DAP>;
+ };
+
+ mas_crypto_c0: mas-crypto-c0 {
+ cell-id = <MSM_BUS_MASTER_CRYPTO_CORE0>;
+ label = "mas-crypto-c0";
+ qcom,buswidth = <650>;
+ qcom,agg-ports = <1>;
+ qcom,connections = <&slv_cr_virt_a2noc>;
+ qcom,bus-dev = <&fab_a2noc>;
+ qcom,mas-rpm-id = <ICBID_MASTER_CRYPTO_CORE0>;
+ };
+
+ mas_apps_proc: mas-apps-proc {
+ cell-id = <MSM_BUS_MASTER_AMPSS_M0>;
+ label = "mas-apps-proc";
+ qcom,buswidth = <32>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,connections = <&slv_gnoc_bimc>;
+ qcom,bus-dev = <&fab_gnoc>;
+ qcom,mas-rpm-id = <ICBID_MASTER_APPSS_PROC>;
+ };
+
+ mas_cnoc_mnoc_mmss_cfg: mas-cnoc-mnoc-mmss-cfg {
+ cell-id = <MSM_BUS_MASTER_CNOC_MNOC_MMSS_CFG>;
+ label = "mas-cnoc-mnoc-mmss-cfg";
+ qcom,buswidth = <8>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,connections = < &slv_camera_throttle_cfg
+ &slv_venus_cfg &slv_misc_cfg
+ &slv_camera_cfg &slv_display_throttle_cfg
+ &slv_venus_throttle_cfg &slv_display_cfg
+ &slv_mmss_clk_cfg &slv_vmem_cfg
+ &slv_mmss_clk_xpu_cfg &slv_smmu_cfg>;
+ qcom,bus-dev = <&fab_mnoc>;
+ qcom,mas-rpm-id = <ICBID_MASTER_CNOC_MNOC_MMSS_CFG>;
+ };
+
+ mas_cnoc_mnoc_cfg: mas-cnoc-mnoc-cfg {
+ cell-id = <MSM_BUS_MASTER_CNOC_MNOC_CFG>;
+ label = "mas-cnoc-mnoc-cfg";
+ qcom,buswidth = <8>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,connections = <&slv_srvc_mnoc>;
+ qcom,bus-dev = <&fab_mnoc>;
+ qcom,mas-rpm-id = <ICBID_MASTER_CNOC_MNOC_CFG>;
+ };
+
+ mas_cpp: mas-cpp {
+ cell-id = <MSM_BUS_MASTER_CPP>;
+ label = "mas-cpp";
+ qcom,buswidth = <32>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,qport = <5>;
+ qcom,qos-mode = "bypass";
+ qcom,connections = <&slv_mnoc_bimc>;
+ qcom,bus-dev = <&fab_mnoc>;
+ qcom,mas-rpm-id = <ICBID_MASTER_CPP>;
+ };
+
+ mas_jpeg: mas-jpeg {
+ cell-id = <MSM_BUS_MASTER_JPEG>;
+ label = "mas-jpeg";
+ qcom,buswidth = <32>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,qport = <7>;
+ qcom,qos-mode = "bypass";
+ qcom,connections = <&slv_mnoc_bimc>;
+ qcom,bus-dev = <&fab_mnoc>;
+ qcom,mas-rpm-id = <ICBID_MASTER_JPEG>;
+ };
+
+ mas_mdp_p0: mas-mdp-p0 {
+ cell-id = <MSM_BUS_MASTER_MDP_PORT0>;
+ label = "mas-mdp-p0";
+ qcom,buswidth = <32>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,qport = <1>;
+ qcom,qos-mode = "bypass";
+ qcom,connections = <&slv_mnoc_bimc>;
+ qcom,bus-dev = <&fab_mnoc>;
+ qcom,mas-rpm-id = <ICBID_MASTER_MDP0>;
+ };
+
+ mas_mdp_p1: mas-mdp-p1 {
+ cell-id = <MSM_BUS_MASTER_MDP_PORT1>;
+ label = "mas-mdp-p1";
+ qcom,buswidth = <32>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,qport = <2>;
+ qcom,qos-mode = "bypass";
+ qcom,connections = <&slv_mnoc_bimc>;
+ qcom,bus-dev = <&fab_mnoc>;
+ qcom,mas-rpm-id = <ICBID_MASTER_MDP1>;
+ };
+
+ mas_rotator: mas-rotator {
+ cell-id = <MSM_BUS_MASTER_ROTATOR>;
+ label = "mas-rotator";
+ qcom,buswidth = <32>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,qport = <0>;
+ qcom,qos-mode = "bypass";
+ qcom,connections = <&slv_mnoc_bimc>;
+ qcom,bus-dev = <&fab_mnoc>;
+ qcom,mas-rpm-id = <ICBID_MASTER_ROTATOR>;
+ };
+
+ mas_venus: mas-venus {
+ cell-id = <MSM_BUS_MASTER_VIDEO_P0>;
+ label = "mas-venus";
+ qcom,buswidth = <32>;
+ qcom,agg-ports = <2>;
+ qcom,ap-owned;
+ qcom,qport = <3 4>;
+ qcom,qos-mode = "bypass";
+ qcom,connections = <&slv_mnoc_bimc>;
+ qcom,bus-dev = <&fab_mnoc>;
+ qcom,mas-rpm-id = <ICBID_MASTER_VIDEO>;
+ };
+
+ mas_vfe: mas-vfe {
+ cell-id = <MSM_BUS_MASTER_VFE>;
+ label = "mas-vfe";
+ qcom,buswidth = <32>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,qport = <6>;
+ qcom,qos-mode = "bypass";
+ qcom,connections = <&slv_mnoc_bimc>;
+ qcom,bus-dev = <&fab_mnoc>;
+ qcom,mas-rpm-id = <ICBID_MASTER_VFE>;
+ };
+
+ mas_hmss: mas-hmss {
+ cell-id = <MSM_BUS_MASTER_HMSS>;
+ label = "mas-hmss";
+ qcom,buswidth = <16>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,qport = <3>;
+ qcom,qos-mode = "fixed";
+ qcom,connections = < &slv_pimem &slv_imem
+ &slv_snoc_bimc>;
+ qcom,prio1 = <1>;
+ qcom,prio0 = <1>;
+ qcom,bus-dev = <&fab_snoc>;
+ qcom,mas-rpm-id = <ICBID_MASTER_HMSS>;
+ };
+
+ mas_qdss_bam: mas-qdss-bam {
+ cell-id = <MSM_BUS_MASTER_QDSS_BAM>;
+ label = "mas-qdss-bam";
+ qcom,buswidth = <16>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,qport = <1>;
+ qcom,qos-mode = "fixed";
+ qcom,connections = < &slv_imem &slv_pimem &slv_snoc_cnoc
+ &slv_snoc_bimc>;
+ qcom,prio1 = <1>;
+ qcom,prio0 = <1>;
+ qcom,bus-dev = <&fab_snoc>;
+ qcom,mas-rpm-id = <ICBID_MASTER_QDSS_BAM>;
+ };
+
+ mas_snoc_cfg: mas-snoc-cfg {
+ cell-id = <MSM_BUS_MASTER_SNOC_CFG>;
+ label = "mas-snoc-cfg";
+ qcom,buswidth = <16>;
+ qcom,agg-ports = <1>;
+ qcom,connections = <&slv_srvc_snoc>;
+ qcom,bus-dev = <&fab_snoc>;
+ qcom,mas-rpm-id = <ICBID_MASTER_SNOC_CFG>;
+ };
+
+ mas_bimc_snoc_0: mas-bimc-snoc-0 {
+ cell-id = <MSM_BUS_BIMC_SNOC_MAS>;
+ label = "mas-bimc-snoc-0";
+ qcom,buswidth = <16>;
+ qcom,agg-ports = <1>;
+ qcom,connections = < &slv_pimem &slv_lpass&slv_hmss
+ &slv_wlan &slv_snoc_cnoc
+ &slv_imem &slv_qdss_stm>;
+ qcom,bus-dev = <&fab_snoc>;
+ qcom,mas-rpm-id = <ICBID_MASTER_BIMC_SNOC_0>;
+ };
+
+ mas_bimc_snoc_1: mas-bimc-snoc-1 {
+ cell-id = <MSM_BUS_BIMC_SNOC_1_MAS>;
+ label = "mas-bimc-snoc-1";
+ qcom,buswidth = <16>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,connections = <&slv_pcie_0>;
+ qcom,bus-dev = <&fab_snoc>;
+ qcom,mas-rpm-id = <ICBID_MASTER_BIMC_SNOC_1>;
+ };
+
+ mas_a1noc_snoc: mas-a1noc-snoc {
+ cell-id = <MSM_BUS_A1NOC_SNOC_MAS>;
+ label = "mas-a1noc-snoc";
+ qcom,buswidth = <16>;
+ qcom,agg-ports = <1>;
+ qcom,connections = < &slv_pimem &slv_pcie_0 &slv_lpass
+ &slv_hmss &slv_snoc_bimc
+ &slv_snoc_cnoc &slv_imem
+ &slv_qdss_stm>;
+ qcom,bus-dev = <&fab_snoc>;
+ qcom,mas-rpm-id = <ICBID_MASTER_A1NOC_SNOC>;
+ };
+
+ mas_a2noc_snoc: mas-a2noc-snoc {
+ cell-id = <MSM_BUS_A2NOC_SNOC_MAS>;
+ label = "mas-a2noc-snoc";
+ qcom,buswidth = <16>;
+ qcom,agg-ports = <1>;
+ qcom,connections = < &slv_pimem &slv_pcie_0 &slv_lpass
+ &slv_hmss &slv_snoc_bimc
+ &slv_wlan &slv_snoc_cnoc
+ &slv_imem &slv_qdss_stm>;
+ qcom,bus-dev = <&fab_snoc>;
+ qcom,mas-rpm-id = <ICBID_MASTER_A2NOC_SNOC>;
+ };
+
+ mas_qdss_etr: mas-qdss-etr {
+ cell-id = <MSM_BUS_MASTER_QDSS_ETR>;
+ label = "mas-qdss-etr";
+ qcom,buswidth = <16>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,qport = <2>;
+ qcom,qos-mode = "fixed";
+ qcom,connections = < &slv_imem &slv_pimem &slv_snoc_cnoc
+ &slv_snoc_bimc>;
+ qcom,prio1 = <1>;
+ qcom,prio0 = <1>;
+ qcom,bus-dev = <&fab_snoc>;
+ qcom,mas-rpm-id = <ICBID_MASTER_QDSS_ETR>;
+ };
+
+ /*Internal nodes*/
+
+ /*Slaves*/
+
+ slv_a1noc_snoc:slv-a1noc-snoc {
+ cell-id = <MSM_BUS_A1NOC_SNOC_SLV>;
+ label = "slv-a1noc-snoc";
+ qcom,buswidth = <16>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_a1noc>;
+ qcom,connections = <&mas_a1noc_snoc>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_A1NOC_SNOC>;
+ };
+
+ slv_a2noc_snoc:slv-a2noc-snoc {
+ cell-id = <MSM_BUS_A2NOC_SNOC_SLV>;
+ label = "slv-a2noc-snoc";
+ qcom,buswidth = <16>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_a2noc>;
+ qcom,connections = <&mas_a2noc_snoc>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_A2NOC_SNOC>;
+ };
+
+ slv_ebi:slv-ebi {
+ cell-id = <MSM_BUS_SLAVE_EBI_CH0>;
+ label = "slv-ebi";
+ qcom,buswidth = <8>;
+ qcom,agg-ports = <2>;
+ qcom,bus-dev = <&fab_bimc>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_EBI1>;
+ };
+
+ slv_hmss_l3:slv-hmss-l3 {
+ cell-id = <MSM_BUS_SLAVE_HMSS_L3>;
+ label = "slv-hmss-l3";
+ qcom,buswidth = <8>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_bimc>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_HMSS_L3>;
+ };
+
+ slv_bimc_snoc_0:slv-bimc-snoc-0 {
+ cell-id = <MSM_BUS_BIMC_SNOC_SLV>;
+ label = "slv-bimc-snoc-0";
+ qcom,buswidth = <8>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_bimc>;
+ qcom,connections = <&mas_bimc_snoc_0>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_BIMC_SNOC_0>;
+ };
+
+ slv_bimc_snoc_1:slv-bimc-snoc-1 {
+ cell-id = <MSM_BUS_BIMC_SNOC_1_SLV>;
+ label = "slv-bimc-snoc-1";
+ qcom,buswidth = <8>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,bus-dev = <&fab_bimc>;
+ qcom,connections = <&mas_bimc_snoc_1>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_BIMC_SNOC_1>;
+ };
+
+ slv_cnoc_a2noc:slv-cnoc-a2noc {
+ cell-id = <MSM_BUS_CNOC_SNOC_SLV>;
+ label = "slv-cnoc-a2noc";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,bus-dev = <&fab_cnoc>;
+ qcom,connections = <&mas_cnoc_a2noc>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_CNOC_A2NOC>;
+ };
+
+ slv_ssc_cfg:slv-ssc-cfg {
+ cell-id = <MSM_BUS_SLAVE_SSC_CFG>;
+ label = "slv-ssc-cfg";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,bus-dev = <&fab_cnoc>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_SSC_CFG>;
+ };
+
+ slv_mpm:slv-mpm {
+ cell-id = <MSM_BUS_SLAVE_MPM>;
+ label = "slv-mpm";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,bus-dev = <&fab_cnoc>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_MPM>;
+ };
+
+ slv_pmic_arb:slv-pmic-arb {
+ cell-id = <MSM_BUS_SLAVE_PMIC_ARB>;
+ label = "slv-pmic-arb";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,bus-dev = <&fab_cnoc>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_PMIC_ARB>;
+ };
+ slv_tlmm_north:slv-tlmm-north {
+ cell-id = <MSM_BUS_SLAVE_TLMM_NORTH>;
+ label = "slv-tlmm-north";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,bus-dev = <&fab_cnoc>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_TLMM_NORTH>;
+ };
+ slv_pimem_cfg:slv-pimem-cfg {
+ cell-id = <MSM_BUS_SLAVE_PIMEM_CFG>;
+ label = "slv-pimem-cfg";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,bus-dev = <&fab_cnoc>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_PIMEM_CFG>;
+ };
+
+ slv_imem_cfg:slv-imem-cfg {
+ cell-id = <MSM_BUS_SLAVE_IMEM_CFG>;
+ label = "slv-imem-cfg";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,bus-dev = <&fab_cnoc>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_IMEM_CFG>;
+ };
+
+ slv_message_ram:slv-message-ram {
+ cell-id = <MSM_BUS_SLAVE_MESSAGE_RAM>;
+ label = "slv-message-ram";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,bus-dev = <&fab_cnoc>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_MESSAGE_RAM>;
+ };
+
+ slv_skl:slv-skl {
+ cell-id = <MSM_BUS_SLAVE_SKL>;
+ label = "slv-skl";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,bus-dev = <&fab_cnoc>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_SKL>;
+ };
+
+ slv_bimc_cfg:slv-bimc-cfg {
+ cell-id = <MSM_BUS_SLAVE_BIMC_CFG>;
+ label = "slv-bimc-cfg";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,bus-dev = <&fab_cnoc>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_BIMC_CFG>;
+ };
+
+ slv_prng:slv-prng {
+ cell-id = <MSM_BUS_SLAVE_PRNG>;
+ label = "slv-prng";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,bus-dev = <&fab_cnoc>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_PRNG>;
+ };
+
+ slv_a2noc_cfg:slv-a2noc-cfg {
+ cell-id = <MSM_BUS_SLAVE_A2NOC_CFG>;
+ label = "slv-a2noc-cfg";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,bus-dev = <&fab_cnoc>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_A2NOC_CFG>;
+ };
+
+ slv_ipa:slv-ipa {
+ cell-id = <MSM_BUS_SLAVE_IPA_CFG>;
+ label = "slv-ipa";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,bus-dev = <&fab_cnoc>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_IPA_CFG>;
+ };
+
+ slv_tcsr:slv-tcsr {
+ cell-id = <MSM_BUS_SLAVE_TCSR>;
+ label = "slv-tcsr";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,bus-dev = <&fab_cnoc>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_TCSR>;
+ };
+
+ slv_snoc_cfg:slv-snoc-cfg {
+ cell-id = <MSM_BUS_SLAVE_SNOC_CFG>;
+ label = "slv-snoc-cfg";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,bus-dev = <&fab_cnoc>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_SNOC_CFG>;
+ };
+
+ slv_clk_ctl:slv-clk-ctl {
+ cell-id = <MSM_BUS_SLAVE_CLK_CTL>;
+ label = "slv-clk-ctl";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,bus-dev = <&fab_cnoc>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_CLK_CTL>;
+ };
+
+ slv_glm:slv-glm {
+ cell-id = <MSM_BUS_SLAVE_GLM>;
+ label = "slv-glm";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,bus-dev = <&fab_cnoc>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_GLM>;
+ };
+
+ slv_spdm:slv-spdm {
+ cell-id = <MSM_BUS_SLAVE_SPDM_WRAPPER>;
+ label = "slv-spdm";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,bus-dev = <&fab_cnoc>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_SPDM_WRAPPER>;
+ };
+
+ slv_gpuss_cfg:slv-gpuss-cfg {
+ cell-id = <MSM_BUS_SLAVE_GRAPHICS_3D_CFG>;
+ label = "slv-gpuss-cfg";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,bus-dev = <&fab_cnoc>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_GFX3D_CFG>;
+ };
+
+ slv_cnoc_mnoc_cfg:slv-cnoc-mnoc-cfg {
+ cell-id = <MSM_BUS_SLAVE_CNOC_MNOC_CFG>;
+ label = "slv-cnoc-mnoc-cfg";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,bus-dev = <&fab_cnoc>;
+ qcom,connections = <&mas_cnoc_mnoc_cfg>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_CNOC_MNOC_CFG>;
+ };
+
+ slv_qm_cfg:slv-qm-cfg {
+ cell-id = <MSM_BUS_SLAVE_QM_CFG>;
+ label = "slv-qm-cfg";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,bus-dev = <&fab_cnoc>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_QM_CFG>;
+ };
+
+ slv_mss_cfg:slv-mss-cfg {
+ cell-id = <MSM_BUS_SLAVE_CNOC_MSS>;
+ label = "slv-mss-cfg";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,bus-dev = <&fab_cnoc>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_CNOC_MSS>;
+ };
+
+ slv_ufs_cfg:slv-ufs-cfg {
+ cell-id = <MSM_BUS_SLAVE_UFS_CFG>;
+ label = "slv-ufs-cfg";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,bus-dev = <&fab_cnoc>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_UFS_CFG>;
+ };
+
+ slv_tlmm_west:slv-tlmm-west {
+ cell-id = <MSM_BUS_SLAVE_TLMM_WEST>;
+ label = "slv-tlmm-west";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,bus-dev = <&fab_cnoc>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_TLMM_WEST>;
+ };
+
+ slv_a1noc_cfg:slv-a1noc-cfg {
+ cell-id = <MSM_BUS_SLAVE_A1NOC_CFG>;
+ label = "slv-a1noc-cfg";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,bus-dev = <&fab_cnoc>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_A1NOC_CFG>;
+ };
+
+ slv_ahb2phy:slv-ahb2phy {
+ cell-id = <MSM_BUS_SLAVE_PCIE20_AHB2PHY>;
+ label = "slv-ahb2phy";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,bus-dev = <&fab_cnoc>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_PCIE20_AHB2PHY>;
+ };
+
+ slv_blsp_2:slv-blsp-2 {
+ cell-id = <MSM_BUS_SLAVE_BLSP_2>;
+ label = "slv-blsp-2";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,bus-dev = <&fab_cnoc>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_BLSP_2>;
+ };
+
+ slv_pdm:slv-pdm {
+ cell-id = <MSM_BUS_SLAVE_PDM>;
+ label = "slv-pdm";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,bus-dev = <&fab_cnoc>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_PDM>;
+ };
+
+ slv_usb3_0:slv-usb3-0 {
+ cell-id = <MSM_BUS_SLAVE_USB3>;
+ label = "slv-usb3-0";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,bus-dev = <&fab_cnoc>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_USB3_0>;
+ };
+
+ slv_a1noc_smmu_cfg:slv-a1noc-smmu-cfg {
+ cell-id = <MSM_BUS_SLAVE_A1NOC_SMMU_CFG>;
+ label = "slv-a1noc-smmu-cfg";
+ qcom,buswidth = <8>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,bus-dev = <&fab_cnoc>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_A1NOC_SMMU_CFG>;
+ };
+
+ slv_blsp_1:slv-blsp-1 {
+ cell-id = <MSM_BUS_SLAVE_BLSP_1>;
+ label = "slv-blsp-1";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,bus-dev = <&fab_cnoc>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_BLSP_1>;
+ };
+
+ slv_sdcc_2:slv-sdcc-2 {
+ cell-id = <MSM_BUS_SLAVE_SDCC_2>;
+ label = "slv-sdcc-2";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,bus-dev = <&fab_cnoc>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_SDCC_2>;
+ };
+
+ slv_sdcc_4:slv-sdcc-4 {
+ cell-id = <MSM_BUS_SLAVE_SDCC_4>;
+ label = "slv-sdcc-4";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,bus-dev = <&fab_cnoc>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_SDCC_4>;
+ };
+
+ slv_tsif:slv-tsif {
+ cell-id = <MSM_BUS_SLAVE_TSIF>;
+ label = "slv-tsif";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,bus-dev = <&fab_cnoc>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_TSIF>;
+ };
+
+ slv_qdss_cfg:slv-qdss-cfg {
+ cell-id = <MSM_BUS_SLAVE_QDSS_CFG>;
+ label = "slv-qdss-cfg";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,bus-dev = <&fab_cnoc>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_QDSS_CFG>;
+ };
+
+ slv_tlmm_east:slv-tlmm-east {
+ cell-id = <MSM_BUS_SLAVE_TLMM_EAST>;
+ label = "slv-tlmm-east";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,bus-dev = <&fab_cnoc>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_TLMM_EAST>;
+ };
+
+ slv_cnoc_mnoc_mmss_cfg:slv-cnoc-mnoc-mmss-cfg {
+ cell-id = <MSM_BUS_SLAVE_CNOC_MNOC_MMSS_CFG>;
+ label = "slv-cnoc-mnoc-mmss-cfg";
+ qcom,buswidth = <8>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,bus-dev = <&fab_cnoc>;
+ qcom,connections = <&mas_cnoc_mnoc_mmss_cfg>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_CNOC_MNOC_MMSS_CFG>;
+ };
+
+ slv_srvc_cnoc:slv-srvc-cnoc {
+ cell-id = <MSM_BUS_SLAVE_SERVICE_CNOC>;
+ label = "slv-srvc-cnoc";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,bus-dev = <&fab_cnoc>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_SERVICE_CNOC>;
+ };
+
+ slv_cr_virt_a2noc:slv-cr-virt-a2noc {
+ cell-id = <MSM_BUS_SLAVE_CRVIRT_A2NOC>;
+ label = "slv-cr-virt-a2noc";
+ qcom,buswidth = <8>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,bus-dev = <&fab_a2noc>;
+ qcom,connections = <&mas_cr_virt_a2noc>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_CRVIRT_A2NOC>;
+ };
+
+ slv_gnoc_bimc:slv-gnoc-bimc {
+ cell-id = <MSM_BUS_SLAVE_GNOC_BIMC>;
+ label = "slv-gnoc-bimc";
+ qcom,buswidth = <32>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,bus-dev = <&fab_gnoc>;
+ qcom,connections = <&mas_gnoc_bimc>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_GNOC_BIMC>;
+ };
+
+ slv_camera_cfg:slv-camera-cfg {
+ cell-id = <MSM_BUS_SLAVE_CAMERA_CFG>;
+ label = "slv-camera-cfg";
+ qcom,buswidth = <8>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,bus-dev = <&fab_mnoc>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_CAMERA_CFG>;
+ };
+
+ slv_camera_throttle_cfg:slv-camera-throttle-cfg {
+ cell-id = <MSM_BUS_SLAVE_CAMERA_THROTTLE_CFG>;
+ label = "slv-camera-throttle-cfg";
+ qcom,buswidth = <8>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,bus-dev = <&fab_mnoc>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_CAMERA_THROTTLE_CFG>;
+ };
+
+ slv_misc_cfg:slv-misc-cfg {
+ cell-id = <MSM_BUS_SLAVE_MISC_CFG>;
+ label = "slv-misc-cfg";
+ qcom,buswidth = <8>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,bus-dev = <&fab_mnoc>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_MISC_CFG>;
+ };
+
+ slv_venus_throttle_cfg:slv-venus-throttle-cfg {
+ cell-id = <MSM_BUS_SLAVE_VENUS_THROTTLE_CFG>;
+ label = "slv-venus-throttle-cfg";
+ qcom,buswidth = <8>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,bus-dev = <&fab_mnoc>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_VENUS_THROTTLE_CFG>;
+ };
+
+ slv_venus_cfg:slv-venus-cfg {
+ cell-id = <MSM_BUS_SLAVE_VENUS_CFG>;
+ label = "slv-venus-cfg";
+ qcom,buswidth = <8>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,bus-dev = <&fab_mnoc>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_VENUS_CFG>;
+ };
+
+ slv_vmem_cfg:slv-vmem-cfg {
+ cell-id = <MSM_BUS_SLAVE_VMEM_CFG>;
+ label = "slv-vmem-cfg";
+ qcom,buswidth = <8>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,bus-dev = <&fab_mnoc>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_VMEM_CFG>;
+ };
+
+ slv_mmss_clk_xpu_cfg:slv-mmss-clk-xpu-cfg {
+ cell-id = <MSM_BUS_SLAVE_MMSS_CLK_XPU_CFG>;
+ label = "slv-mmss-clk-xpu-cfg";
+ qcom,buswidth = <8>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,bus-dev = <&fab_mnoc>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_MMSS_CLK_XPU_CFG>;
+ };
+
+ slv_mmss_clk_cfg:slv-mmss-clk-cfg {
+ cell-id = <MSM_BUS_SLAVE_MMSS_CLK_CFG>;
+ label = "slv-mmss-clk-cfg";
+ qcom,buswidth = <8>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,bus-dev = <&fab_mnoc>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_MMSS_CLK_CFG>;
+ };
+
+ slv_display_cfg:slv-display-cfg {
+ cell-id = <MSM_BUS_SLAVE_DISPLAY_CFG>;
+ label = "slv-display-cfg";
+ qcom,buswidth = <8>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,bus-dev = <&fab_mnoc>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_DISPLAY_CFG>;
+ };
+
+ slv_display_throttle_cfg:slv-display-throttle-cfg {
+ cell-id = <MSM_BUS_SLAVE_DISPLAY_THROTTLE_CFG>;
+ label = "slv-display-throttle-cfg";
+ qcom,buswidth = <8>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,bus-dev = <&fab_mnoc>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_DISPLAY_THROTTLE_CFG>;
+ };
+
+ slv_smmu_cfg:slv-smmu-cfg {
+ cell-id = <MSM_BUS_SLAVE_MMSS_SMMU_CFG>;
+ label = "slv-smmu-cfg";
+ qcom,buswidth = <8>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,bus-dev = <&fab_mnoc>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_MMSS_SMMU_CFG>;
+ };
+
+ slv_mnoc_bimc:slv-mnoc-bimc {
+ cell-id = <MSM_BUS_MNOC_BIMC_SLV>;
+ label = "slv-mnoc-bimc";
+ qcom,buswidth = <32>;
+ qcom,agg-ports = <2>;
+ qcom,ap-owned;
+ qcom,bus-dev = <&fab_mnoc>;
+ qcom,connections = <&mas_mnoc_bimc>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_MNOC_BIMC>;
+ };
+
+ slv_srvc_mnoc:slv-srvc-mnoc {
+ cell-id = <MSM_BUS_SLAVE_SERVICE_MNOC>;
+ label = "slv-srvc-mnoc";
+ qcom,buswidth = <8>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,bus-dev = <&fab_mnoc>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_SERVICE_MNOC>;
+ };
+
+ slv_hmss:slv-hmss {
+ cell-id = <MSM_BUS_SLAVE_APPSS>;
+ label = "slv-hmss";
+ qcom,buswidth = <16>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,bus-dev = <&fab_snoc>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_APPSS>;
+ };
+
+ slv_lpass:slv-lpass {
+ cell-id = <MSM_BUS_SLAVE_LPASS>;
+ label = "slv-lpass";
+ qcom,buswidth = <16>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,bus-dev = <&fab_snoc>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_LPASS>;
+ };
+
+ slv_wlan:slv-wlan {
+ cell-id = <MSM_BUS_SLAVE_WLAN>;
+ label = "slv-wlan";
+ qcom,buswidth = <16>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_snoc>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_WLAN>;
+ };
+
+ slv_snoc_bimc:slv-snoc-bimc {
+ cell-id = <MSM_BUS_SNOC_BIMC_SLV>;
+ label = "slv-snoc-bimc";
+ qcom,buswidth = <32>;
+ qcom,agg-ports = <2>;
+ qcom,bus-dev = <&fab_snoc>;
+ qcom,connections = <&mas_snoc_bimc>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_SNOC_BIMC>;
+ };
+
+ slv_snoc_cnoc:slv-snoc-cnoc {
+ cell-id = <MSM_BUS_SNOC_CNOC_SLV>;
+ label = "slv-snoc-cnoc";
+ qcom,buswidth = <16>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_snoc>;
+ qcom,connections = <&mas_snoc_cnoc>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_SNOC_CNOC>;
+ };
+
+ slv_imem:slv-imem {
+ cell-id = <MSM_BUS_SLAVE_OCIMEM>;
+ label = "slv-imem";
+ qcom,buswidth = <16>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_snoc>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_IMEM>;
+ };
+
+ slv_pimem:slv-pimem {
+ cell-id = <MSM_BUS_SLAVE_PIMEM>;
+ label = "slv-pimem";
+ qcom,buswidth = <16>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_snoc>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_PIMEM>;
+ };
+
+ slv_qdss_stm:slv-qdss-stm {
+ cell-id = <MSM_BUS_SLAVE_QDSS_STM>;
+ label = "slv-qdss-stm";
+ qcom,buswidth = <16>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_snoc>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_QDSS_STM>;
+ };
+
+ slv_pcie_0:slv-pcie-0 {
+ cell-id = <MSM_BUS_SLAVE_PCIE_0>;
+ label = "slv-pcie-0";
+ qcom,buswidth = <16>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,bus-dev = <&fab_snoc>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_PCIE_0>;
+ };
+
+ slv_srvc_snoc:slv-srvc-snoc {
+ cell-id = <MSM_BUS_SLAVE_SERVICE_SNOC>;
+ label = "slv-srvc-snoc";
+ qcom,buswidth = <16>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_snoc>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_SERVICE_SNOC>;
+ };
+ };
+};
--- /dev/null
+/*
+ * Copyright (c) 2015-2016, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+&soc {
+ qcom,msm-cam@8c0000 {
+ compatible = "qcom,msm-cam";
+ reg = <0x8c0000 0x40000>;
+ reg-names = "msm-cam";
+ status = "ok";
+ bus-vectors = "suspend", "svs", "nominal", "turbo";
+ qcom,bus-votes = <0 300000000 640000000 640000000>;
+ };
+
+ qcom,cam_smmu {
+ compatible = "qcom,msm-cam-smmu";
+
+ msm_cam_smmu_cb1 {
+ compatible = "qcom,msm-cam-smmu-cb";
+ iommus = <&mmss_smmu 0xc00>,
+ <&mmss_smmu 0xc01>,
+ <&mmss_smmu 0xc02>,
+ <&mmss_smmu 0xc03>;
+ label = "vfe";
+ qcom,scratch-buf-support;
+ };
+
+ msm_cam_smmu_cb2 {
+ compatible = "qcom,msm-cam-smmu-cb";
+ iommus = <&mmss_smmu 0xa00>;
+ label = "cpp";
+ };
+
+ msm_cam_smmu_cb3 {
+ compatible = "qcom,msm-cam-smmu-cb";
+ iommus = <&mmss_smmu 0xa01>;
+ label = "camera_fd";
+ };
+
+ msm_cam_smmu_cb4 {
+ compatible = "qcom,msm-cam-smmu-cb";
+ iommus = <&mmss_smmu 0x800>;
+ label = "jpeg_enc0";
+ };
+
+ msm_cam_smmu_cb5 {
+ compatible = "qcom,msm-cam-smmu-cb";
+ iommus = <&mmss_smmu 0x801>;
+ label = "jpeg_dma";
+ };
+ };
+
+ qcom,fd@caa4000 {
+ cell-index = <0>;
+ compatible = "qcom,face-detection";
+ reg = <0xcaa4000 0x800>,
+ <0xcaa5000 0x400>,
+ <0xca80000 0x3000>;
+ reg-names = "fd_core", "fd_misc", "fd_vbif";
+ interrupts = <0 293 0>;
+ interrupt-names = "fd";
+ smmu-vdd-supply = <&gdsc_bimc_smmu>;
+ camss-vdd-supply = <&gdsc_camss_top>;
+ qcom,vdd-names = "smmu-vdd", "camss-vdd";
+ clocks = <&clock_mmss clk_mmss_camss_top_ahb_clk>,
+ <&clock_mmss clk_fd_core_clk_src>,
+ <&clock_mmss clk_mmss_fd_core_clk>,
+ <&clock_mmss clk_mmss_fd_core_uar_clk>,
+ <&clock_mmss clk_mmss_fd_ahb_clk>,
+ <&clock_mmss clk_mmss_camss_ahb_clk>,
+ <&clock_mmss clk_mmss_camss_cpp_axi_clk>,
+ <&clock_mmss clk_mmss_camss_cpp_vbif_ahb_clk>;
+ clock-names = "camss_top_ahb_clk",
+ "fd_core_clk_src", "fd_core_clk",
+ "fd_core_uar_clk", "fd_ahb_clk",
+ "camss_ahb_clk", "camss_cpp_axi_clk",
+ "cpp_vbif_ahb_clk";
+ qcom,clock-rates = <0 400000000 400000000>,
+ <0 0 0 0 0>;
+ qcom,msm-bus,name = "msm_camera_fd";
+ qcom,msm-bus,num-cases = <4>;
+ qcom,msm-bus,num-paths = <1>;
+ qcom,msm-bus,vectors-KBps = <106 512 0 0>,
+ <106 512 13000000 13000000>,
+ <106 512 45000000 45000000>,
+ <106 512 90000000 90000000>;
+ qcom,fd-vbif-reg-settings = <0x20 0x10000000 0x30000000>,
+ <0x24 0x10000000 0x30000000>,
+ <0x28 0x10000000 0x30000000>,
+ <0x2c 0x10000000 0x30000000>;
+ qcom,fd-misc-reg-settings = <0x20 0x2 0x3>,
+ <0x24 0x2 0x3>;
+ status = "ok";
+ };
+};
--- /dev/null
+/* Copyright (c) 2016, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+
+/dts-v1/;
+
+#include "msmcobalt.dtsi"
+#include "msmcobalt-cdp.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. MSM cobalt";
+ compatible = "qcom,msmcobalt-cdp", "qcom,msmcobalt", "qcom,cdp";
+ qcom,board-id = <1 0>;
+};
--- /dev/null
+/* Copyright (c) 2016, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include "msmcobalt-pinctrl.dtsi"
--- /dev/null
+/* Copyright (c) 2016, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+&soc {
+ tmc_etr: tmc@6048000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x0003b961>;
+
+ reg = <0x6048000 0x1000>,
+ <0x6064000 0x15000>;
+ reg-names = "tmc-base", "bam-base";
+
+ arm,buffer-size = <0x400000>;
+
+ coresight-name = "coresight-tmc-etr";
+
+ clocks = <&clock_gcc clk_qdss_clk>,
+ <&clock_gcc clk_qdss_a_clk>;
+ clock-names = "apb_pclk", "core_a_clk";
+
+ port{
+ tmc_etr_in_replicator: endpoint {
+ slave-mode;
+ remote-endpoint = <&replicator_out_tmc_etr>;
+ };
+ };
+ };
+
+ replicator: replicator@6046000 {
+ compatible = "arm,coresight-replicator";
+
+ coresight-name = "coresight-replicator";
+
+ ports{
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ replicator_out_tmc_etr:endpoint {
+ remote-endpoint =
+ <&tmc_etr_in_replicator>;
+ };
+ };
+ port@1 {
+ reg = <0>;
+ replicator_in_tmc_etf:endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&tmc_etf_out_replicator>;
+ };
+ };
+ };
+ };
+
+ tmc_etf: tmc@6047000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x0003b961>;
+
+ reg = <0x6047000 0x1000>;
+ reg-names = "tmc-base";
+
+ coresight-name = "coresight-tmc-etf";
+
+ clocks = <&clock_gcc clk_qdss_clk>,
+ <&clock_gcc clk_qdss_a_clk>;
+ clock-names = "apb_pclk", "core_a_clk";
+
+ ports{
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ tmc_etf_out_replicator:endpoint {
+ remote-endpoint =
+ <&replicator_in_tmc_etf>;
+ };
+ };
+ port@1 {
+ reg = <0>;
+ tmc_etf_in_funnel_merg:endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&funnel_merg_out_tmc_etf>;
+ };
+ };
+ };
+ };
+
+ funnel_merg: funnel@6045000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x0003b908>;
+
+ reg = <0x6045000 0x1000>;
+ reg-names = "funnel-base";
+
+ coresight-name = "coresight-funnel-merg";
+
+ clocks = <&clock_gcc clk_qdss_clk>,
+ <&clock_gcc clk_qdss_a_clk>;
+ clock-names = "apb_pclk", "core_a_clk";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ funnel_merg_out_tmc_etf:endpoint {
+ remote-endpoint =
+ <&tmc_etf_in_funnel_merg>;
+ };
+ };
+ port@1 {
+ reg = <0>;
+ funnel_merg_in_funnel_in0:endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&funnel_in0_out_funnel_merg>;
+ };
+ };
+ };
+ };
+
+ funnel_in0: funnel@6041000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x0003b908>;
+
+ reg = <0x6041000 0x1000>;
+ reg-names = "funnel-base";
+
+ coresight-name = "coresight-funnel-in0";
+
+ clocks = <&clock_gcc clk_qdss_clk>,
+ <&clock_gcc clk_qdss_a_clk>;
+ clock-names = "apb_pclk", "core_a_clk";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ funnel_in0_out_funnel_merg: endpoint {
+ remote-endpoint =
+ <&funnel_merg_in_funnel_in0>;
+ };
+ };
+ port@1 {
+ reg = <7>;
+ funnel_in0_in_stm: endpoint {
+ slave-mode;
+ remote-endpoint = <&stm_out_funnel_in0>;
+ };
+ };
+ };
+ };
+
+ stm: stm@6002000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x0003b962>;
+
+ reg = <0x6002000 0x1000>,
+ <0x16280000 0x180000>;
+ reg-names = "stm-base", "stm-data-base";
+
+ coresight-name = "coresight-stm";
+
+ clocks = <&clock_gcc clk_qdss_clk>,
+ <&clock_gcc clk_qdss_a_clk>;
+ clock-names = "apb_pclk", "core_a_clk";
+
+ port{
+ stm_out_funnel_in0: endpoint {
+ remote-endpoint = <&funnel_in0_in_stm>;
+ };
+ };
+ };
+};
--- /dev/null
+/* Copyright (c) 2015, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+&soc {
+ qcom,ion {
+ compatible = "qcom,msm-ion";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ system_heap: qcom,ion-heap@25 {
+ reg = <25>;
+ qcom,ion-heap-type = "SYSTEM";
+ };
+
+ system_contig_heap: qcom,ion-heap@21 {
+ reg = <21>;
+ qcom,ion-heap-type = "SYSTEM_CONTIG";
+ };
+ };
+};
--- /dev/null
+/* Copyright (c) 2016, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+
+/dts-v1/;
+
+#include "msmcobalt.dtsi"
+#include "msmcobalt-mtp.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. MSM cobalt v1";
+ compatible = "qcom,msmcobalt-mtp", "qcom,msmcobalt", "qcom,mtp";
+ qcom,board-id = <8 0>;
+};
--- /dev/null
+/* Copyright (c) 2016, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include "msmcobalt-pinctrl.dtsi"
--- /dev/null
+/* Copyright (c) 2015, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+&soc {
+ tlmm: pinctrl@03400000 {
+ compatible = "qcom,msmcobalt-pinctrl";
+ reg = <0x03400000 0xc00000>;
+ interrupts = <0 208 0>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+
+ uart_console_active: uart_console_active {
+ mux {
+ pins = "gpio4", "gpio5";
+ function = "blsp_uart8_a";
+ };
+
+ config {
+ pins = "gpio4", "gpio5";
+ drive-strength = <2>;
+ bias-disable;
+ };
+ };
+ };
+};
--- /dev/null
+/* Copyright (c) 2016, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+&soc {
+ qcom,lpm-levels {
+ compatible = "qcom,lpm-levels";
+ qcom,use-psci;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ qcom,pm-cluster@0 {
+ reg = <0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ label = "system";
+ qcom,spm-device-names = "cci";
+ qcom,psci-mode-shift = <8>;
+ qcom,psci-mode-mask = <0xf>;
+
+ qcom,pm-cluster-level@0{
+ reg = <0>;
+ label = "system-wfi";
+ qcom,psci-mode = <0x0>;
+ qcom,latency-us = <100>;
+ qcom,ss-power = <725>;
+ qcom,energy-overhead = <85000>;
+ qcom,time-overhead = <120>;
+ };
+
+ qcom,pm-cluster-level@1{ /* E3 */
+ reg = <1>;
+ label = "system-ret";
+ qcom,spm-cbf-mode = "pc";
+ qcom,spm-l3-mode = "pc";
+ qcom,psci-mode = <0x3>;
+ qcom,latency-us = <350>;
+ qcom,ss-power = <530>;
+ qcom,energy-overhead = <160000>;
+ qcom,time-overhead = <550>;
+ qcom,min-child-idx = <1>;
+ qcom,is-reset;
+ };
+
+ qcom,pm-cluster@0{
+ reg = <0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ label = "pwr";
+ qcom,spm-device-names = "l2";
+ qcom,cpu = <&CPU0 &CPU1 &CPU2 &CPU3>;
+ qcom,psci-mode-shift = <4>;
+ qcom,psci-mode-mask = <0xf>;
+
+ qcom,pm-cluster-level@0{ /* D1 */
+ reg = <0>;
+ label = "pwr-l2-wfi";
+ qcom,psci-mode = <0x1>;
+ qcom,latency-us = <40>;
+ qcom,ss-power = <740>;
+ qcom,energy-overhead = <65000>;
+ qcom,time-overhead = <85>;
+ };
+
+ qcom,pm-cluster-level@1{ /* D4 */
+ reg = <1>;
+ label = "pwr-l2-pc";
+ qcom,psci-mode = <0x4>;
+ qcom,latency-us = <700>;
+ qcom,ss-power = <450>;
+ qcom,energy-overhead = <210000>;
+ qcom,time-overhead = <11500>;
+ qcom,min-child-idx = <1>;
+ qcom,is-reset;
+ };
+
+ qcom,pm-cpu {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ qcom,psci-mode-shift = <0>;
+ qcom,psci-mode-mask = <0xf>;
+
+ qcom,pm-cpu-level@0 { /* C1 */
+ reg = <0>;
+ qcom,spm-cpu-mode = "wfi";
+ qcom,psci-cpu-mode = <0x1>;
+ qcom,latency-us = <20>;
+ qcom,ss-power = <750>;
+ qcom,energy-overhead = <32000>;
+ qcom,time-overhead = <60>;
+ };
+
+ qcom,pm-cpu-level@1 { /* C3 */
+ reg = <1>;
+ qcom,spm-cpu-mode = "pc";
+ qcom,psci-cpu-mode = <0x3>;
+ qcom,latency-us = <80>;
+ qcom,ss-power = <700>;
+ qcom,energy-overhead = <126480>;
+ qcom,time-overhead = <160>;
+ qcom,is-reset;
+ };
+ };
+ };
+
+ qcom,pm-cluster@1{
+ reg = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ label = "perf";
+ qcom,spm-device-names = "l2";
+ qcom,cpu = <&CPU4 &CPU5 &CPU6 &CPU7>;
+ qcom,psci-mode-shift = <4>;
+ qcom,psci-mode-mask = <0xf>;
+
+ qcom,pm-cluster-level@0{ /* D1 */
+ reg = <0>;
+ label = "perf-l2-wfi";
+ qcom,psci-mode = <0x1>;
+ qcom,latency-us = <40>;
+ qcom,ss-power = <740>;
+ qcom,energy-overhead = <70000>;
+ qcom,time-overhead = <80>;
+ };
+
+ qcom,pm-cluster-level@1{ /* D4 */
+ reg = <1>;
+ label = "perf-l2-pc";
+ qcom,psci-mode = <0x4>;
+ qcom,latency-us = <800>;
+ qcom,ss-power = <450>;
+ qcom,energy-overhead = <240000>;
+ qcom,time-overhead = <11500>;
+ qcom,min-child-idx = <1>;
+ qcom,is-reset;
+ };
+
+ qcom,pm-cpu {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ qcom,psci-mode-shift = <0>;
+ qcom,psci-mode-mask = <0xf>;
+
+ qcom,pm-cpu-level@0 { /* C1 */
+ reg = <0>;
+ qcom,spm-cpu-mode = "wfi";
+ qcom,psci-cpu-mode = <0x1>;
+ qcom,latency-us = <25>;
+ qcom,ss-power = <750>;
+ qcom,energy-overhead = <37000>;
+ qcom,time-overhead = <50>;
+ };
+
+ qcom,pm-cpu-level@1 { /* C3 */
+ reg = <1>;
+ qcom,spm-cpu-mode = "pc";
+ qcom,psci-cpu-mode = <0x3>;
+ qcom,latency-us = <80>;
+ qcom,ss-power = <700>;
+ qcom,energy-overhead = <136480>;
+ qcom,time-overhead = <160>;
+ qcom,is-reset;
+ };
+ };
+ };
+ };
+ };
+};
--- /dev/null
+/* Copyright (c) 2015, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+&rpm_bus {
+ /* PMCOBALT S1 + S6 = VDD_CX supply */
+ rpm-regulator-smpa1 {
+ status = "okay";
+ pmcobalt_s1_level: regulator-s1-level {
+ compatible = "qcom,rpm-smd-regulator";
+ regulator-name = "pmcobalt_s1_level";
+ qcom,set = <3>;
+ regulator-min-microvolt =
+ <RPM_SMD_REGULATOR_LEVEL_RETENTION>;
+ regulator-max-microvolt =
+ <RPM_SMD_REGULATOR_LEVEL_TURBO>;
+ qcom,use-voltage-level;
+ };
+
+ pmcobalt_s1_floor_level: regulator-s1-floor-level {
+ compatible = "qcom,rpm-smd-regulator";
+ regulator-name = "pmcobalt_s1_floor_level";
+ qcom,set = <3>;
+ regulator-min-microvolt =
+ <RPM_SMD_REGULATOR_LEVEL_RETENTION>;
+ regulator-max-microvolt =
+ <RPM_SMD_REGULATOR_LEVEL_TURBO>;
+ qcom,use-voltage-floor-level;
+ qcom,always-send-voltage;
+ };
+
+ pmcobalt_s1_level_ao: regulator-s1-level-ao {
+ compatible = "qcom,rpm-smd-regulator";
+ regulator-name = "pmcobalt_s1_level_ao";
+ qcom,set = <1>;
+ regulator-min-microvolt =
+ <RPM_SMD_REGULATOR_LEVEL_RETENTION>;
+ regulator-max-microvolt =
+ <RPM_SMD_REGULATOR_LEVEL_TURBO>;
+ qcom,use-voltage-level;
+ };
+ };
+
+ rpm-regulator-smpa2 {
+ status = "okay";
+ pmcobalt_s2: regulator-s2 {
+ regulator-min-microvolt = <1128000>;
+ regulator-max-microvolt = <1128000>;
+ status = "okay";
+ };
+ };
+
+ rpm-regulator-smpa3 {
+ status = "okay";
+ pmcobalt_s3: regulator-s3 {
+ regulator-min-microvolt = <1352000>;
+ regulator-max-microvolt = <1352000>;
+ status = "okay";
+ };
+ };
+
+ rpm-regulator-smpa4 {
+ status = "okay";
+ pmcobalt_s4: regulator-s4 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ status = "okay";
+ };
+ };
+
+ rpm-regulator-smpa5 {
+ status = "okay";
+ pmcobalt_s5: regulator-s5 {
+ regulator-min-microvolt = <2040000>;
+ regulator-max-microvolt = <2040000>;
+ status = "okay";
+ };
+ };
+
+ rpm-regulator-smpa7 {
+ status = "okay";
+ pmcobalt_s7: regulator-s7 {
+ regulator-min-microvolt = <1028000>;
+ regulator-max-microvolt = <1028000>;
+ status = "okay";
+ };
+ };
+
+ rpm-regulator-smpa8 {
+ status = "okay";
+ pmcobalt_s8: regulator-s8 {
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <800000>;
+ status = "okay";
+ };
+ };
+
+ /* PMCOBALT S9 = VDD_MX supply */
+ rpm-regulator-smpa9 {
+ status = "okay";
+ pmcobalt_s9_level: regulator-s9-level {
+ compatible = "qcom,rpm-smd-regulator";
+ regulator-name = "pmcobalt_s9_level";
+ qcom,set = <3>;
+ regulator-min-microvolt =
+ <RPM_SMD_REGULATOR_LEVEL_RETENTION>;
+ regulator-max-microvolt =
+ <RPM_SMD_REGULATOR_LEVEL_TURBO>;
+ qcom,use-voltage-level;
+ };
+
+ pmcobalt_s9_floor_level: regulator-s9-floor-level {
+ compatible = "qcom,rpm-smd-regulator";
+ regulator-name = "pmcobalt_s9_floor_level";
+ qcom,set = <3>;
+ regulator-min-microvolt =
+ <RPM_SMD_REGULATOR_LEVEL_RETENTION>;
+ regulator-max-microvolt =
+ <RPM_SMD_REGULATOR_LEVEL_TURBO>;
+ qcom,use-voltage-floor-level;
+ qcom,always-send-voltage;
+ };
+
+ pmcobalt_s9_level_ao: regulator-s9-level-ao {
+ compatible = "qcom,rpm-smd-regulator";
+ regulator-name = "pmcobalt_s9_level_ao";
+ qcom,set = <1>;
+ regulator-min-microvolt =
+ <RPM_SMD_REGULATOR_LEVEL_RETENTION>;
+ regulator-max-microvolt =
+ <RPM_SMD_REGULATOR_LEVEL_TURBO>;
+ qcom,use-voltage-level;
+ };
+ };
+
+ rpm-regulator-ldoa1 {
+ status = "okay";
+ pmcobalt_l1: regulator-l1 {
+ regulator-min-microvolt = <880000>;
+ regulator-max-microvolt = <880000>;
+ status = "okay";
+ };
+ };
+
+ rpm-regulator-ldoa2 {
+ status = "okay";
+ pmcobalt_l2: regulator-l2 {
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ status = "okay";
+ };
+ };
+
+ rpm-regulator-ldoa3 {
+ status = "okay";
+ pmcobalt_l3: regulator-l3 {
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1000000>;
+ status = "okay";
+ };
+ };
+
+ /* PMCOBALT L4 = VDD_SSC_MX supply */
+ rpm-regulator-ldoa4 {
+ status = "okay";
+ pmcobalt_l4_level: regulator-l4-level {
+ compatible = "qcom,rpm-smd-regulator";
+ regulator-name = "pmcobalt_l4_level";
+ qcom,set = <3>;
+ regulator-min-microvolt =
+ <RPM_SMD_REGULATOR_LEVEL_RETENTION>;
+ regulator-max-microvolt =
+ <RPM_SMD_REGULATOR_LEVEL_TURBO>;
+ qcom,use-voltage-level;
+ };
+
+ pmcobalt_l4_floor_level: regulator-l4-floor-level {
+ compatible = "qcom,rpm-smd-regulator";
+ regulator-name = "pmcobalt_l4_floor_level";
+ qcom,set = <3>;
+ regulator-min-microvolt =
+ <RPM_SMD_REGULATOR_LEVEL_RETENTION>;
+ regulator-max-microvolt =
+ <RPM_SMD_REGULATOR_LEVEL_TURBO>;
+ qcom,use-voltage-floor-level;
+ qcom,always-send-voltage;
+ };
+ };
+
+ rpm-regulator-ldoa5 {
+ status = "okay";
+ pmcobalt_l5: regulator-l5 {
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <800000>;
+ status = "okay";
+ };
+ };
+
+ rpm-regulator-ldoa6 {
+ status = "okay";
+ pmcobalt_l6: regulator-l6 {
+ regulator-min-microvolt = <1808000>;
+ regulator-max-microvolt = <1808000>;
+ status = "okay";
+ };
+ };
+
+ rpm-regulator-ldoa7 {
+ status = "okay";
+ pmcobalt_l7: regulator-l7 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ status = "okay";
+ };
+ };
+
+ rpm-regulator-ldoa8 {
+ status = "okay";
+ pmcobalt_l8: regulator-l8 {
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ status = "okay";
+ };
+ };
+
+ rpm-regulator-ldoa9 {
+ status = "okay";
+ pmcobalt_l9: regulator-l9 {
+ regulator-min-microvolt = <1808000>;
+ regulator-max-microvolt = <2960000>;
+ status = "okay";
+ };
+ };
+
+ rpm-regulator-ldoa10 {
+ status = "okay";
+ pmcobalt_l10: regulator-l10 {
+ regulator-min-microvolt = <1808000>;
+ regulator-max-microvolt = <2960000>;
+ status = "okay";
+ };
+ };
+
+ rpm-regulator-ldoa11 {
+ status = "okay";
+ pmcobalt_l11: regulator-l11 {
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1000000>;
+ status = "okay";
+ };
+ };
+
+ rpm-regulator-ldoa12 {
+ status = "okay";
+ pmcobalt_l12: regulator-l12 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ status = "okay";
+ };
+ };
+
+ rpm-regulator-ldoa13 {
+ status = "okay";
+ pmcobalt_l13: regulator-l13 {
+ regulator-min-microvolt = <1808000>;
+ regulator-max-microvolt = <2960000>;
+ status = "okay";
+ };
+ };
+
+ rpm-regulator-ldoa14 {
+ status = "okay";
+ pmcobalt_l14: regulator-l14 {
+ regulator-min-microvolt = <1880000>;
+ regulator-max-microvolt = <1880000>;
+ status = "okay";
+ };
+ };
+
+ rpm-regulator-ldoa15 {
+ status = "okay";
+ pmcobalt_l15: regulator-l15 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ status = "okay";
+ };
+ };
+
+ rpm-regulator-ldoa16 {
+ status = "okay";
+ pmcobalt_l16: regulator-l16 {
+ regulator-min-microvolt = <2704000>;
+ regulator-max-microvolt = <2704000>;
+ status = "okay";
+ };
+ };
+
+ rpm-regulator-ldoa17 {
+ status = "okay";
+ pmcobalt_l17: regulator-l17 {
+ regulator-min-microvolt = <1304000>;
+ regulator-max-microvolt = <1304000>;
+ status = "okay";
+ };
+ };
+
+ rpm-regulator-ldoa18 {
+ status = "okay";
+ pmcobalt_l18: regulator-l18 {
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ status = "okay";
+ };
+ };
+
+ rpm-regulator-ldoa19 {
+ status = "okay";
+ pmcobalt_l19: regulator-l19 {
+ regulator-min-microvolt = <3008000>;
+ regulator-max-microvolt = <3008000>;
+ status = "okay";
+ };
+ };
+
+ rpm-regulator-ldoa20 {
+ status = "okay";
+ pmcobalt_l20: regulator-l20 {
+ regulator-min-microvolt = <2960000>;
+ regulator-max-microvolt = <2960000>;
+ status = "okay";
+ };
+ };
+
+ rpm-regulator-ldoa21 {
+ status = "okay";
+ pmcobalt_l21: regulator-l21 {
+ regulator-min-microvolt = <2960000>;
+ regulator-max-microvolt = <2960000>;
+ status = "okay";
+ };
+ };
+
+ rpm-regulator-ldoa22 {
+ status = "okay";
+ pmcobalt_l22: regulator-l22 {
+ regulator-min-microvolt = <3312000>;
+ regulator-max-microvolt = <3312000>;
+ status = "okay";
+ };
+ };
+
+ rpm-regulator-ldoa23 {
+ status = "okay";
+ pmcobalt_l23: regulator-l23 {
+ regulator-min-microvolt = <3312000>;
+ regulator-max-microvolt = <3312000>;
+ status = "okay";
+ };
+ };
+
+ rpm-regulator-ldoa24 {
+ status = "okay";
+ pmcobalt_l24: regulator-l24 {
+ regulator-min-microvolt = <3088000>;
+ regulator-max-microvolt = <3088000>;
+ status = "okay";
+ };
+ };
+ rpm-regulator-ldoa25 {
+ status = "okay";
+ pmcobalt_l25: regulator-l25 {
+ regulator-min-microvolt = <3312000>;
+ regulator-max-microvolt = <3312000>;
+ status = "okay";
+ };
+ };
+
+ rpm-regulator-ldoa26 {
+ status = "okay";
+ pmcobalt_l26: regulator-l26 {
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ status = "okay";
+ };
+ };
+
+ /* PMCOBALT L27 = VDD_SSC_CX supply */
+ rpm-regulator-ldoa27 {
+ status = "okay";
+ pmcobalt_l27_level: regulator-l27-level {
+ compatible = "qcom,rpm-smd-regulator";
+ regulator-name = "pmcobalt_l27_level";
+ qcom,set = <3>;
+ regulator-min-microvolt =
+ <RPM_SMD_REGULATOR_LEVEL_RETENTION>;
+ regulator-max-microvolt =
+ <RPM_SMD_REGULATOR_LEVEL_TURBO>;
+ qcom,use-voltage-level;
+ };
+
+ pmcobalt_l27_floor_level: regulator-l27-floor-level {
+ compatible = "qcom,rpm-smd-regulator";
+ regulator-name = "pmcobalt_l27_floor_level";
+ qcom,set = <3>;
+ regulator-min-microvolt =
+ <RPM_SMD_REGULATOR_LEVEL_RETENTION>;
+ regulator-max-microvolt =
+ <RPM_SMD_REGULATOR_LEVEL_TURBO>;
+ qcom,use-voltage-floor-level;
+ qcom,always-send-voltage;
+ };
+ };
+
+ rpm-regulator-ldoa28 {
+ status = "okay";
+ pmcobalt_l28: regulator-l28 {
+ regulator-min-microvolt = <3008000>;
+ regulator-max-microvolt = <3008000>;
+ status = "okay";
+ };
+ };
+
+ rpm-regulator-vsa1 {
+ status = "okay";
+ pmcobalt_lvs1: regulator-lvs1 {
+ status = "okay";
+ };
+ };
+
+ rpm-regulator-vsa2 {
+ status = "okay";
+ pmcobalt_lvs2: regulator-lvs2 {
+ status = "okay";
+ };
+ };
+
+ rpm-regulator-bobb {
+ status = "okay";
+ pmicobalt_bob: regulator-bob {
+ regulator-min-microvolt = <3312000>;
+ regulator-max-microvolt = <3600000>;
+ status = "okay";
+ };
+ pmicobalt_bob_pin1: regulator-bob-pin1 {
+ compatible = "qcom,rpm-smd-regulator";
+ regulator-name = "pmcobalt_bob_pin1";
+ qcom,set = <3>;
+ regulator-min-microvolt = <3312000>;
+ regulator-max-microvolt = <3600000>;
+ qcom,use-pin-ctrl-voltage1;
+ };
+ pmicobalt_bob_pin2: regulator-bob-pin2 {
+ compatible = "qcom,rpm-smd-regulator";
+ regulator-name = "pmcobalt_bob_pin2";
+ qcom,set = <3>;
+ regulator-min-microvolt = <3312000>;
+ regulator-max-microvolt = <3600000>;
+ qcom,use-pin-ctrl-voltage2;
+ };
+ pmicobalt_bob_pin3: regulator-bob-pin3 {
+ compatible = "qcom,rpm-smd-regulator";
+ regulator-name = "pmcobalt_bob_pin3";
+ qcom,set = <3>;
+ regulator-min-microvolt = <3312000>;
+ regulator-max-microvolt = <3600000>;
+ qcom,use-pin-ctrl-voltage3;
+ };
+ };
+};
+
+/* Stub regulators */
+
+/ {
+
+ /* PMCOBALT S10 = APC_0 supply */
+ pmcobalt_s10: regulator-pmcobalt-s10 {
+ compatible = "qcom,stub-regulator";
+ regulator-name = "pmcobalt_s10";
+ qcom,hpm-min-load = <100000>;
+ regulator-min-microvolt = <352000>;
+ regulator-max-microvolt = <952000>;
+ };
+
+ /*
+ * PMCOBALT S11 + S12 + S13 = 3 phase APC_1 supply
+ * S13 is the gang leader
+ */
+ pmcobalt_s13: regulator-pmcobalt-s13 {
+ compatible = "qcom,stub-regulator";
+ regulator-name = "pmcobalt_s13";
+ qcom,hpm-min-load = <100000>;
+ regulator-min-microvolt = <352000>;
+ regulator-max-microvolt = <952000>;
+ };
+
+ /* PM8005 S1 + S4 = 2 phase VDD_GFX supply */
+ pm8005_s1: regulator-pm8005-s1 {
+ compatible = "qcom,stub-regulator";
+ regulator-name = "pm8005_s1";
+ qcom,hpm-min-load = <100000>;
+ regulator-min-microvolt = <352000>;
+ regulator-max-microvolt = <952000>;
+ };
+
+ /* PM8005 S2 = VDD_MODEM supply */
+ pm8005_s2: regulator-pm8005-s2 {
+ compatible = "qcom,stub-regulator";
+ regulator-name = "pm8005_s2";
+ qcom,hpm-min-load = <100000>;
+ regulator-min-microvolt = <352000>;
+ regulator-max-microvolt = <952000>;
+ };
+
+ pm8005_s3: regulator-pm8005-s3 {
+ compatible = "qcom,stub-regulator";
+ regulator-name = "pm8005_s3";
+ qcom,hpm-min-load = <100000>;
+ regulator-min-microvolt = <600000>;
+ regulator-max-microvolt = <600000>;
+ };
+};
+
--- /dev/null
+/* Copyright (c) 2015-2016, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+
+/dts-v1/;
+/memreserve/ 0x90000000 0x00000100;
+
+#include "msmcobalt.dtsi"
+#include "msmcobalt-rumi.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. MSM COBALT RUMI";
+ compatible = "qcom,msmcobalt-rumi", "qcom,msmcobalt", "qcom,rumi";
+ qcom,board-id = <15 0>;
+};
+
+&usb3 {
+ qcom,disable-dev-mode-pm;
+ dwc3@a800000 {
+ maximum-speed = "high-speed";
+ };
+};
+
+&wdog {
+ status = "disabled";
+};
+
+&qusb_phy0 {
+ reg = <0x0a928000 0x8000>,
+ <0x0a8f8800 0x400>,
+ <0x0a920000 0x100>;
+ reg-names = "qusb_phy_base",
+ "qscratch_base",
+ "emu_phy_base";
+ qcom,emulation;
+ qcom,emu-init-seq = <0x7f 0x4
+ 0x0 0x4
+ 0x3ff 0x28
+ 0x1f 0x2c>;
+ qcom,qusb-phy-init-seq = <0x19 0x1404
+ 0x20 0x1414
+ 0x79 0x1410
+ 0x00 0x1418
+ 0x99 0x1404
+ 0x04 0x1408
+ 0xd9 0x1404>;
+ qcom,phy-pll-reset-seq = <0x80000000 0x7500
+ 0x0 0x7500
+ 0x201e0 0x7500
+ 0x0 0x7500>;
+ qcom,emu-dcm-reset-seq = <0x100000 0x20
+ 0x0 0x20
+ 0x1e0 0x20
+ 0x5 0x14>;
+};
+
+&ssphy {
+ compatible = "usb-nop-xceiv";
+};
--- /dev/null
+/* Copyright (c) 2015-2016, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include "msmcobalt-pinctrl.dtsi"
+&uartblsp2dm1 {
+ status = "ok";
+};
+
+&ufsphy1 {
+ compatible = "qcom,ufs-phy-qrbtc-v2";
+ reg = <0x1da7000 0xda8>, /* PHY regs */
+ <0x1db8000 0x100>; /* U11 user regs */
+ reg-names = "phy_mem", "u11_user";
+ vdda-phy-supply = <&pmcobalt_l28>;
+ vdda-pll-supply = <&pmcobalt_l2>;
+ vddp-ref-clk-supply = <&pmcobalt_l26>;
+ status = "ok";
+};
+
+&ufs1 {
+ vcc-supply = <&pmcobalt_l20>;
+ vccq-supply = <&pmcobalt_l26>;
+ vccq2-supply = <&pmcobalt_s4>;
+ status = "ok";
+};
+
+&ufs_ice {
+ status = "ok";
+};
+
+&sdhc_2 {
+ vdd-supply = <&pmcobalt_l21>;
+ qcom,vdd-voltage-level = <2950000 2960000>;
+ qcom,vdd-current-level = <200 800000>;
+
+ vdd-io-supply = <&pmcobalt_l13>;
+ qcom,vdd-io-voltage-level = <1800000 2950000>;
+ qcom,vdd-io-current-level = <200 22000>;
+
+ qcom,clk-rates = <400000 20000000 25000000
+ 50000000 100000000 200000000>;
+ qcom,bus-speed-mode = "SDR12", "SDR25", "SDR50", "DDR50", "SDR104";
+
+ status = "ok";
+};
+
+&soc {
+ qcom,icnss@18800000 {
+ compatible = "qcom,icnss";
+ reg = <0x18800000 0x800000>;
+ reg-names = "membase";
+ interrupts =
+ <0 413 0 /* CE0 */ >,
+ <0 414 0 /* CE1 */ >,
+ <0 415 0 /* CE2 */ >,
+ <0 416 0 /* CE3 */ >,
+ <0 417 0 /* CE4 */ >,
+ <0 418 0 /* CE5 */ >,
+ <0 420 0 /* CE6 */ >,
+ <0 421 0 /* CE7 */ >,
+ <0 422 0 /* CE8 */ >,
+ <0 423 0 /* CE9 */ >,
+ <0 424 0 /* CE10 */ >,
+ <0 425 0 /* CE11 */ >;
+ };
+};
+
+&gdsc_ufs {
+ compatible = "regulator-fixed";
+};
--- /dev/null
+/* Copyright (c) 2015, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+
+/dts-v1/;
+/memreserve/ 0x90000000 0x00000100;
+
+#include "msmcobalt.dtsi"
+#include "msmcobalt-sim.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. MSM COBALT SIM";
+ compatible = "qcom,msmcobalt-sim", "qcom,msmcobalt", "qcom,sim";
+ qcom,board-id = <16 0>;
+};
+
+&ufsphy1 {
+ status = "ok";
+};
+
+&ufs1 {
+ status = "ok";
+};
+
+&ufs_ice {
+ status = "ok";
+};
+
+&qusb_phy0 {
+ compatible = "usb-nop-xceiv";
+};
+
+&ssphy {
+ compatible = "usb-nop-xceiv";
+};
--- /dev/null
+/* Copyright (c) 2015, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include "msmcobalt-pinctrl.dtsi"
+
+&uartblsp2dm1 {
+ status = "ok";
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart_console_active>;
+};
--- /dev/null
+/* Copyright (c) 2015, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+&soc {
+ qcom,smp2p-modem@17911008 {
+ compatible = "qcom,smp2p";
+ reg = <0x17911008 0x4>;
+ qcom,remote-pid = <1>;
+ qcom,irq-bitmask = <0x4000>;
+ interrupts = <0 451 1>;
+ };
+
+ qcom,smp2p-adsp@17911008 {
+ compatible = "qcom,smp2p";
+ reg = <0x17911008 0x4>;
+ qcom,remote-pid = <2>;
+ qcom,irq-bitmask = <0x400>;
+ interrupts = <0 158 1>;
+ };
+
+ qcom,smp2p-dsps@17911008 {
+ compatible = "qcom,smp2p";
+ reg = <0x17911008 0x4>;
+ qcom,remote-pid = <3>;
+ qcom,irq-bitmask = <0x4000000>;
+ interrupts = <0 178 1>;
+ };
+
+ smp2pgpio_smp2p_15_in: qcom,smp2pgpio-smp2p-15-in {
+ compatible = "qcom,smp2pgpio";
+ qcom,entry-name = "smp2p";
+ qcom,remote-pid = <15>;
+ qcom,is-inbound;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ qcom,smp2pgpio_test_smp2p_15_in {
+ compatible = "qcom,smp2pgpio_test_smp2p_15_in";
+ gpios = <&smp2pgpio_smp2p_15_in 0 0>;
+ };
+
+ smp2pgpio_smp2p_15_out: qcom,smp2pgpio-smp2p-15-out {
+ compatible = "qcom,smp2pgpio";
+ qcom,entry-name = "smp2p";
+ qcom,remote-pid = <15>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ qcom,smp2pgpio_test_smp2p_15_out {
+ compatible = "qcom,smp2pgpio_test_smp2p_15_out";
+ gpios = <&smp2pgpio_smp2p_15_out 0 0>;
+ };
+
+ smp2pgpio_smp2p_1_in: qcom,smp2pgpio-smp2p-1-in {
+ compatible = "qcom,smp2pgpio";
+ qcom,entry-name = "smp2p";
+ qcom,remote-pid = <1>;
+ qcom,is-inbound;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ qcom,smp2pgpio_test_smp2p_1_in {
+ compatible = "qcom,smp2pgpio_test_smp2p_1_in";
+ gpios = <&smp2pgpio_smp2p_1_in 0 0>;
+ };
+
+ smp2pgpio_smp2p_1_out: qcom,smp2pgpio-smp2p-1-out {
+ compatible = "qcom,smp2pgpio";
+ qcom,entry-name = "smp2p";
+ qcom,remote-pid = <1>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ qcom,smp2pgpio_test_smp2p_1_out {
+ compatible = "qcom,smp2pgpio_test_smp2p_1_out";
+ gpios = <&smp2pgpio_smp2p_1_out 0 0>;
+ };
+
+ smp2pgpio_smp2p_2_in: qcom,smp2pgpio-smp2p-2-in {
+ compatible = "qcom,smp2pgpio";
+ qcom,entry-name = "smp2p";
+ qcom,remote-pid = <2>;
+ qcom,is-inbound;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ qcom,smp2pgpio_test_smp2p_2_in {
+ compatible = "qcom,smp2pgpio_test_smp2p_2_in";
+ gpios = <&smp2pgpio_smp2p_2_in 0 0>;
+ };
+
+ smp2pgpio_smp2p_2_out: qcom,smp2pgpio-smp2p-2-out {
+ compatible = "qcom,smp2pgpio";
+ qcom,entry-name = "smp2p";
+ qcom,remote-pid = <2>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ qcom,smp2pgpio_test_smp2p_2_out {
+ compatible = "qcom,smp2pgpio_test_smp2p_2_out";
+ gpios = <&smp2pgpio_smp2p_2_out 0 0>;
+ };
+
+ smp2pgpio_smp2p_3_in: qcom,smp2pgpio-smp2p-3-in {
+ compatible = "qcom,smp2pgpio";
+ qcom,entry-name = "smp2p";
+ qcom,remote-pid = <3>;
+ qcom,is-inbound;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ qcom,smp2pgpio_test_smp2p_3_in {
+ compatible = "qcom,smp2pgpio_test_smp2p_3_in";
+ gpios = <&smp2pgpio_smp2p_3_in 0 0>;
+ };
+
+ smp2pgpio_smp2p_3_out: qcom,smp2pgpio-smp2p-3-out {
+ compatible = "qcom,smp2pgpio";
+ qcom,entry-name = "smp2p";
+ qcom,remote-pid = <3>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ /* ssr - inbound entry from mss */
+ smp2pgpio_ssr_smp2p_1_in: qcom,smp2pgpio-ssr-smp2p-1-in {
+ compatible = "qcom,smp2pgpio";
+ qcom,entry-name = "slave-kernel";
+ qcom,remote-pid = <1>;
+ qcom,is-inbound;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ /* ssr - outbound entry to mss */
+ smp2pgpio_ssr_smp2p_1_out: qcom,smp2pgpio-ssr-smp2p-1-out {
+ compatible = "qcom,smp2pgpio";
+ qcom,entry-name = "master-kernel";
+ qcom,remote-pid = <1>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ /* ssr - inbound entry from lpass */
+ smp2pgpio_ssr_smp2p_2_in: qcom,smp2pgpio-ssr-smp2p-2-in {
+ compatible = "qcom,smp2pgpio";
+ qcom,entry-name = "slave-kernel";
+ qcom,remote-pid = <2>;
+ qcom,is-inbound;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ /* ssr - outbound entry to lpass */
+ smp2pgpio_ssr_smp2p_2_out: qcom,smp2pgpio-ssr-smp2p-2-out {
+ compatible = "qcom,smp2pgpio";
+ qcom,entry-name = "master-kernel";
+ qcom,remote-pid = <2>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ /* ssr - inbound entry from ssc */
+ smp2pgpio_ssr_smp2p_3_in: qcom,smp2pgpio-ssr-smp2p-3-in {
+ compatible = "qcom,smp2pgpio";
+ qcom,entry-name = "slave-kernel";
+ qcom,remote-pid = <3>;
+ qcom,is-inbound;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ /* ssr - outbound entry to ssc */
+ smp2pgpio_ssr_smp2p_3_out: qcom,smp2pgpio-ssr-smp2p-3-out {
+ compatible = "qcom,smp2pgpio";
+ qcom,entry-name = "master-kernel";
+ qcom,remote-pid = <3>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ qcom,smp2pgpio_test_smp2p_3_out {
+ compatible = "qcom,smp2pgpio_test_smp2p_3_out";
+ gpios = <&smp2pgpio_smp2p_3_out 0 0>;
+ };
+
+ smp2pgpio_sleepstate_3_out: qcom,smp2pgpio-sleepstate-gpio-3-out {
+ compatible = "qcom,smp2pgpio";
+ qcom,entry-name = "sleepstate";
+ qcom,remote-pid = <3>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ qcom,smp2pgpio-sleepstate-3-out {
+ compatible = "qcom,smp2pgpio_sleepstate_3_out";
+ gpios = <&smp2pgpio_sleepstate_3_out 0 0>;
+ };
+};
--- /dev/null
+/* Copyright (c) 2016, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+
+/dts-v1/;
+
+#include "msmcobalt-v2.dtsi"
+#include "msmcobalt-cdp.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. MSM cobalt v2";
+ compatible = "qcom,msmcobalt-cdp", "qcom,msmcobalt", "qcom,cdp";
+ qcom,board-id = <1 0>;
+};
--- /dev/null
+/* Copyright (c) 2016, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+
+/dts-v1/;
+
+#include "msmcobalt-v2.dtsi"
+#include "msmcobalt-mtp.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. MSM cobalt v2";
+ compatible = "qcom,msmcobalt-mtp", "qcom,msmcobalt", "qcom,mtp";
+ qcom,board-id = <8 0>;
+};
--- /dev/null
+/* Copyright (c) 2016, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+
+/dts-v1/;
+/memreserve/ 0x90000000 0x00000100;
+
+#include "msmcobalt-v2.dtsi"
+#include "msmcobalt-rumi.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. MSM COBALT V2 RUMI";
+ compatible = "qcom,msmcobalt-rumi", "qcom,msmcobalt", "qcom,rumi";
+ qcom,board-id = <15 0>;
+};
--- /dev/null
+/* Copyright (c) 2016, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+
+/dts-v1/;
+/memreserve/ 0x90000000 0x00000100;
+
+#include "msmcobalt-v2.dtsi"
+#include "msmcobalt-sim.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. MSM COBALT V2 SIM";
+ compatible = "qcom,msmcobalt-sim", "qcom,msmcobalt", "qcom,sim";
+ qcom,board-id = <16 0>;
+};
--- /dev/null
+/* Copyright (c) 2016 The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/*
+ * As a general rule, only version-specific property overrides should be placed
+ * inside this file. Common device definitions should be placed inside the
+ * msmcobalt.dtsi file.
+ */
+
+#include "msmcobalt.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. MSMCOBALT v2";
+ qcom,msm-id = <292 0x20000>;
+};
+
--- /dev/null
+/* Copyright (c) 2014-2016, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/msm/msm-bus-ids.h>
+
+&soc {
+ msm_vidc: qcom,vidc@cc00000 {
+ compatible = "qcom,msm-vidc";
+ status = "disabled";
+ reg = <0xcc00000 0x100000>;
+ interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
+ qcom,max-hw-load = <2563200>; /* Full 4k @ 60 + 1080p @ 60 */
+ qcom,hfi = "venus";
+ qcom,hfi-version = "3xx";
+ qcom,firmware-name = "venus";
+ };
+
+ qcom,vmem@c880000 {
+ compatible = "qcom,msm-vmem";
+ status = "disabled";
+ interrupts = <GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH>;
+
+ reg = <0xc880000 0x6b>,
+ <0x14800000 0x80000>;
+ reg-names = "reg-base", "mem-base";
+
+ clocks = <&clock_mmss clk_mmss_vmem_ahb_clk>,
+ <&clock_mmss clk_mmss_vmem_maxi_clk>;
+ clock-names = "ahb", "maxi";
+
+ qcom,msm-bus,name = "vmem";
+ qcom,msm-bus,num-cases = <2>;
+ qcom,msm-bus,num-paths = <1>;
+ qcom,msm-bus,vectors-KBps =
+ <MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_VMEM_CFG 0 0>,
+ <MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_VMEM_CFG 500 800>;
+
+ qcom,bank-size = <524288>; /* 512 kB */
+ };
+};
--- /dev/null
+/* Copyright (c) 2015-2016, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include "skeleton64.dtsi"
+#include <dt-bindings/clock/msm-clocks-cobalt.h>
+#include <dt-bindings/regulator/qcom,rpm-smd-regulator.h>
+
+/ {
+ model = "Qualcomm Technologies, Inc. MSM COBALT";
+ compatible = "qcom,msmcobalt";
+ qcom,msm-id = <292 0x0>;
+ interrupt-parent = <&intc>;
+
+ aliases {
+ serial0 = &uartblsp2dm1;
+ sdhc2 = &sdhc_2; /* SDC2 SD card slot */
+ };
+
+ psci {
+ compatible = "arm,psci-1.0";
+ method = "smc";
+ };
+
+ chosen {
+ stdout-path = "serial0";
+ };
+
+ cpus {
+ #address-cells = <2>;
+ #size-cells = <0>;
+
+ CPU0: cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,armv8";
+ reg = <0x0 0x0>;
+ qcom,limits-info = <&mitigation_profile0>;
+ enable-method = "psci";
+ next-level-cache = <&L2_0>;
+ L2_0: l2-cache {
+ compatible = "arm,arch-cache";
+ cache-level = <2>;
+ qcom,dump-size = <0x0>; /* A53 L2 dump not supported */
+ };
+ L1_I_0: l1-icache {
+ compatible = "arm,arch-cache";
+ qcom,dump-size = <0x9040>;
+ };
+ L1_D_0: l1-dcache {
+ compatible = "arm,arch-cache";
+ qcom,dump-size = <0x9040>;
+ };
+ };
+
+ CPU1: cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,armv8";
+ reg = <0x0 0x1>;
+ qcom,limits-info = <&mitigation_profile1>;
+ enable-method = "psci";
+ next-level-cache = <&L2_0>;
+ L1_I_1: l1-icache {
+ compatible = "arm,arch-cache";
+ qcom,dump-size = <0x9040>;
+ };
+ L1_D_1: l1-dcache {
+ compatible = "arm,arch-cache";
+ qcom,dump-size = <0x9040>;
+ };
+ };
+
+ CPU2: cpu@2 {
+ device_type = "cpu";
+ compatible = "arm,armv8";
+ reg = <0x0 0x2>;
+ qcom,limits-info = <&mitigation_profile2>;
+ enable-method = "psci";
+ next-level-cache = <&L2_0>;
+ L1_I_2: l1-icache {
+ compatible = "arm,arch-cache";
+ qcom,dump-size = <0x9040>;
+ };
+ L1_D_2: l1-dcache {
+ compatible = "arm,arch-cache";
+ qcom,dump-size = <0x9040>;
+ };
+ };
+
+ CPU3: cpu@3 {
+ device_type = "cpu";
+ compatible = "arm,armv8";
+ reg = <0x0 0x3>;
+ qcom,limits-info = <&mitigation_profile3>;
+ enable-method = "psci";
+ next-level-cache = <&L2_0>;
+ L1_I_3: l1-icache {
+ compatible = "arm,arch-cache";
+ qcom,dump-size = <0x9040>;
+ };
+ L1_D_3: l1-dcache {
+ compatible = "arm,arch-cache";
+ qcom,dump-size = <0x9040>;
+ };
+ };
+
+ CPU4: cpu@100 {
+ device_type = "cpu";
+ compatible = "arm,armv8";
+ reg = <0x0 0x100>;
+ qcom,limits-info = <&mitigation_profile4>;
+ enable-method = "psci";
+ next-level-cache = <&L2_1>;
+ L2_1: l2-cache {
+ compatible = "arm,arch-cache";
+ cache-level = <2>;
+ };
+ L1_I_100: l1-icache {
+ compatible = "arm,arch-cache";
+ qcom,dump-size = <0x12000>;
+ };
+ L1_D_100: l1-dcache {
+ compatible = "arm,arch-cache";
+ qcom,dump-size = <0x12000>;
+ };
+ };
+
+ CPU5: cpu@101 {
+ device_type = "cpu";
+ compatible = "arm,armv8";
+ reg = <0x0 0x101>;
+ qcom,limits-info = <&mitigation_profile5>;
+ enable-method = "psci";
+ next-level-cache = <&L2_1>;
+ L1_I_101: l1-icache {
+ compatible = "arm,arch-cache";
+ qcom,dump-size = <0x12000>;
+ };
+ L1_D_101: l1-dcache {
+ compatible = "arm,arch-cache";
+ qcom,dump-size = <0x12000>;
+ };
+ };
+
+ CPU6: cpu@102 {
+ device_type = "cpu";
+ compatible = "arm,armv8";
+ reg = <0x0 0x102>;
+ qcom,limits-info = <&mitigation_profile6>;
+ enable-method = "psci";
+ next-level-cache = <&L2_1>;
+ L1_I_102: l1-icache {
+ compatible = "arm,arch-cache";
+ qcom,dump-size = <0x12000>;
+ };
+ L1_D_102: l1-dcache {
+ compatible = "arm,arch-cache";
+ qcom,dump-size = <0x12000>;
+ };
+ };
+
+ CPU7: cpu@103 {
+ device_type = "cpu";
+ compatible = "arm,armv8";
+ reg = <0x0 0x103>;
+ qcom,limits-info = <&mitigation_profile7>;
+ enable-method = "psci";
+ next-level-cache = <&L2_1>;
+ L1_I_103: l1-icache {
+ compatible = "arm,arch-cache";
+ qcom,dump-size = <0x12000>;
+ };
+ L1_D_103: l1-dcache {
+ compatible = "arm,arch-cache";
+ qcom,dump-size = <0x12000>;
+ };
+ };
+
+ cpu-map {
+ cluster0 {
+ core0 {
+ cpu = <&CPU0>;
+ };
+
+ core1 {
+ cpu = <&CPU1>;
+ };
+
+ core2 {
+ cpu = <&CPU2>;
+ };
+
+ core3 {
+ cpu = <&CPU3>;
+ };
+ };
+
+ cluster1 {
+ core0 {
+ cpu = <&CPU4>;
+ };
+
+ core1 {
+ cpu = <&CPU5>;
+ };
+
+ core2 {
+ cpu = <&CPU6>;
+ };
+
+ core3 {
+ cpu = <&CPU7>;
+ };
+ };
+ };
+ };
+
+ soc: soc { };
+
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ removed_regions: removed_regions@85800000 {
+ compatible = "removed-dma-pool";
+ no-map;
+ reg = <0 0x85800000 0 0x4f00000>;
+ };
+
+ peripheral_mem: peripheral_region@91400000 {
+ compatible = "removed-dma-pool";
+ no-map;
+ reg = <0 0x91400000 0 0x2d00000>;
+ };
+
+ modem_mem: modem_region@8a700000 {
+ compatible = "removed-dma-pool";
+ no-map;
+ reg = <0 0x8a700000 0 0x6d00000>;
+ };
+ };
+};
+
+#include "msmcobalt-smp2p.dtsi"
+#include "msm-gdsc-cobalt.dtsi"
+
+&soc {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0 0 0xffffffff>;
+ compatible = "simple-bus";
+
+ intc: interrupt-controller@17a00000 {
+ compatible = "arm,gic-v3";
+ reg = <0x17a00000 0x10000>, /* GICD */
+ <0x17b00000 0x100000>; /* GICR * 8 */
+ #interrupt-cells = <3>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+ interrupt-controller;
+ #redistributor-regions = <1>;
+ redistributor-stride = <0x0 0x20000>;
+ interrupts = <1 9 4>;
+
+ gic-its@0x17a20000{
+ compatible = "arm,gic-v3-its";
+ msi-contoller;
+ reg = <0x17a20000 0x20000>;
+ };
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupts = <1 1 0xf08>,
+ <1 2 0xf08>,
+ <1 3 0xf08>,
+ <1 0 0xf08>;
+ clock-frequency = <19200000>;
+ };
+
+ restart@10ac000 {
+ compatible = "qcom,pshold";
+ reg = <0x10ac000 0x4>,
+ <0x1fd3000 0x4>;
+ reg-names = "pshold-base", "tcsr-boot-misc-detect";
+ };
+
+ uartblsp1dm1: serial@0c170000 {
+ compatible = "qcom,msm-lsuart-v14", "qcom,msm-uartdm";
+ reg = <0xc170000 0x1000>;
+ interrupts = <0 108 0>;
+ status = "disabled";
+ clocks = <&clock_gcc clk_gcc_blsp1_uart2_apps_clk>,
+ <&clock_gcc clk_gcc_blsp1_ahb_clk>;
+ clock-names = "core_clk", "iface_clk";
+ };
+
+ uartblsp2dm1: serial@0c1b0000 {
+ compatible = "qcom,msm-lsuart-v14", "qcom,msm-uartdm";
+ reg = <0xc1b0000 0x1000>;
+ interrupts = <0 114 0>;
+ status = "disabled";
+ clocks = <&clock_gcc clk_gcc_blsp2_uart2_apps_clk>,
+ <&clock_gcc clk_gcc_blsp2_ahb_clk>;
+ clock-names = "core_clk", "iface_clk";
+ };
+
+ timer@17920000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+ compatible = "arm,armv7-timer-mem";
+ reg = <0x17920000 0x1000>;
+ clock-frequency = <19200000>;
+
+ frame@17921000 {
+ frame-number = <0>;
+ interrupts = <0 8 0x4>,
+ <0 7 0x4>;
+ reg = <0x17921000 0x1000>,
+ <0x17922000 0x1000>;
+ };
+
+ frame@17923000 {
+ frame-number = <1>;
+ interrupts = <0 9 0x4>;
+ reg = <0x17923000 0x1000>;
+ status = "disabled";
+ };
+
+ frame@17924000 {
+ frame-number = <2>;
+ interrupts = <0 10 0x4>;
+ reg = <0x17924000 0x1000>;
+ status = "disabled";
+ };
+
+ frame@17925000 {
+ frame-number = <3>;
+ interrupts = <0 11 0x4>;
+ reg = <0x17925000 0x1000>;
+ status = "disabled";
+ };
+
+ frame@17926000 {
+ frame-number = <4>;
+ interrupts = <0 12 0x4>;
+ reg = <0x17926000 0x1000>;
+ status = "disabled";
+ };
+
+ frame@17927000 {
+ frame-number = <5>;
+ interrupts = <0 13 0x4>;
+ reg = <0x17927000 0x1000>;
+ status = "disabled";
+ };
+
+ frame@17928000 {
+ frame-number = <6>;
+ interrupts = <0 14 0x4>;
+ reg = <0x17928000 0x1000>;
+ status = "disabled";
+ };
+ };
+
+ arm64-cpu-erp {
+ compatible = "arm,arm64-cpu-erp";
+ interrupts = <0 43 4>,
+ <0 44 4>,
+ <0 41 4>,
+ <0 42 4>;
+
+ interrupt-names = "pri-dbe-irq",
+ "sec-dbe-irq",
+ "pri-ext-irq",
+ "sec-ext-irq";
+
+ poll-delay-ms = <5000>;
+ };
+
+ clock_gcc: qcom,gcc@100000 {
+ compatible = "qcom,gcc-cobalt";
+ reg = <0x100000 0xb0000>;
+ reg-names = "cc_base";
+ vdd_dig-supply = <&pmcobalt_s1_level>;
+ #clock-cells = <1>;
+ };
+
+ clock_mmss: qcom,mmsscc@c8c0000 {
+ compatible = "qcom,mmsscc-cobalt";
+ reg = <0xc8c0000 0x40000>;
+ reg-names = "cc_base";
+ vdd_dig-supply = <&pmcobalt_s1_level>;
+ clock-names = "xo", "gpll0", "gpll0_div";
+ clocks = <&clock_gcc clk_cxo_clk_src>,
+ <&clock_gcc clk_gpll0_out_main>,
+ <&clock_gcc clk_gcc_mmss_gpll0_div_clk>;
+ #clock-cells = <1>;
+ };
+
+ clock_gpu: qcom,gpucc@5065000 {
+ compatible = "qcom,gpucc-cobalt";
+ reg = <0x5065000 0x9000>;
+ reg-names = "cc_base";
+ vdd_gpucc-supply = <&pm8005_s1>;
+ vdd_dig-supply = <&pmcobalt_s1_level>;
+ vdd_mx-supply = <&pmcobalt_s9_level>;
+ vdd_gpu_mx-supply = <&pmcobalt_s9_level>;
+ clock-names = "xo", "gpll0";
+ clocks = <&clock_gcc clk_cxo_clk_src>,
+ <&clock_gcc clk_gpll0_out_main>;
+ qcom,gfxfreq-speedbin0 =
+ < 0 0 0 >,
+ < 171000000 520000 RPM_SMD_REGULATOR_LEVEL_SVS >,
+ < 251000000 570000 RPM_SMD_REGULATOR_LEVEL_SVS >,
+ < 332000000 630000 RPM_SMD_REGULATOR_LEVEL_SVS >,
+ < 403000000 680000 RPM_SMD_REGULATOR_LEVEL_SVS >,
+ < 504000000 745000 RPM_SMD_REGULATOR_LEVEL_NOM >,
+ < 650000000 855000 RPM_SMD_REGULATOR_LEVEL_TURBO >;
+ qcom,gfxfreq-mx-speedbin0 =
+ < 0 0 >,
+ < 171000000 RPM_SMD_REGULATOR_LEVEL_SVS >,
+ < 251000000 RPM_SMD_REGULATOR_LEVEL_SVS >,
+ < 332000000 RPM_SMD_REGULATOR_LEVEL_SVS >,
+ < 403000000 RPM_SMD_REGULATOR_LEVEL_SVS >,
+ < 504000000 RPM_SMD_REGULATOR_LEVEL_NOM >,
+ < 650000000 RPM_SMD_REGULATOR_LEVEL_TURBO >;
+ #clock-cells = <1>;
+ };
+
+ clock_debug: qcom,debugcc@162000 {
+ compatible = "qcom,cc-debug-cobalt";
+ reg = <0x162000 0x4>;
+ reg-names = "cc_base";
+ clock-names = "debug_gpu_clk", "debug_mmss_clk";
+ clocks = <&clock_gpu clk_gpucc_gcc_dbg_clk>,
+ <&clock_mmss clk_mmss_debug_mux>;
+ #clock-cells = <1>;
+ };
+
+ qcom,msm_gsi {
+ compatible = "qcom,msm_gsi";
+ };
+
+ qcom,rmnet-ipa {
+ compatible = "qcom,rmnet-ipa3";
+ };
+
+ ipa_hw: qcom,ipa@01e00000 {
+ compatible = "qcom,ipa";
+ reg = <0x01e00000 0x34000>,
+ <0x01e84000 0x31fff>,
+ <0x01e04000 0x2c000>;
+ reg-names = "ipa-base", "bam-base", "gsi-base";
+ interrupts =
+ <0 333 0>,
+ <0 432 0>,
+ <0 432 0>;
+ interrupt-names = "ipa-irq", "bam-irq", "gsi-irq";
+ qcom,ipa-hw-ver = <11>; /* IPA core version = IPAv3.1 */
+ qcom,ipa-hw-mode = <0>; /* IPA hw type = Normal */
+ qcom,ee = <0>;
+ qcom,use-gsi;
+ qcom,use-ipa-tethering-bridge;
+ qcom,modem-cfg-emb-pipe-flt;
+ clock-names = "core_clk";
+ clocks = <&clock_gcc clk_ipa_a_clk>;
+ qcom,msm-bus,name = "ipa";
+ qcom,msm-bus,num-cases = <4>;
+ qcom,msm-bus,num-paths = <2>;
+ qcom,msm-bus,vectors-KBps =
+ <90 512 0 0>, <90 585 0 0>, /* No vote */
+ <90 512 80000 640000>, <90 585 80000 640000>, /* SVS */
+ <90 512 206000 960000>, <90 585 206000 960000>, /* NOMINAL */
+ <90 512 206000 3600000>, <90 585 206000 3600000>; /* TURBO */
+ qcom,bus-vector-names = "MIN", "SVS", "NOMINAL", "TURBO";
+ };
+
+ qcom,chd {
+ compatible = "qcom,core-hang-detect";
+ qcom,threshold-arr = <0x179880b0 0x179980b0
+ 0x179a80b0 0x179b80b0 0x178880b0 0x178980b0
+ 0x178a80b0 0x178b80b0>;
+ qcom,config-arr = <0x179880b8 0x179980b8
+ 0x179a80b8 0x179b80b8 0x178880b8 0x178980b8
+ 0x178a80b8 0x178b80b8>;
+ };
+
+ qcom,ipc-spinlock@1f40000 {
+ compatible = "qcom,ipc-spinlock-sfpb";
+ reg = <0x1f40000 0x8000>;
+ qcom,num-locks = <8>;
+ };
+
+ qcom,ghd {
+ compatible = "qcom,gladiator-hang-detect";
+ qcom,threshold-arr = <0x179d141c 0x179d1420
+ 0x179d1424 0x179d1428 0x179d142c 0x179d1430>;
+ qcom,config-reg = <0x179d1434>;
+ };
+
+ qcom,smem@86000000 {
+ compatible = "qcom,smem";
+ reg = <0x86000000 0x200000>,
+ <0x17911008 0x4>,
+ <0x778000 0x7000>,
+ <0x1fd4000 0x8>;
+ reg-names = "smem", "irq-reg-base", "aux-mem1",
+ "smem_targ_info_reg";
+ qcom,mpu-enabled;
+
+ qcom,smd-modem {
+ compatible = "qcom,smd";
+ qcom,smd-edge = <0>;
+ qcom,smd-irq-offset = <0x0>;
+ qcom,smd-irq-bitmask = <0x1000>;
+ interrupts = <0 449 1>;
+ label = "modem";
+ qcom,not-loadable;
+ };
+
+ qcom,smd-adsp {
+ compatible = "qcom,smd";
+ qcom,smd-edge = <1>;
+ qcom,smd-irq-offset = <0x0>;
+ qcom,smd-irq-bitmask = <0x100>;
+ interrupts = <0 156 1>;
+ label = "adsp";
+ };
+
+ qcom,smd-dsps {
+ compatible = "qcom,smd";
+ qcom,smd-edge = <3>;
+ qcom,smd-irq-offset = <0x0>;
+ qcom,smd-irq-bitmask = <0x2000000>;
+ interrupts = <0 176 1>;
+ label = "dsps";
+ };
+ };
+
+ rpm_bus: qcom,rpm-smd {
+ compatible = "qcom,rpm-glink";
+ qcom,glink-edge = "rpm";
+ rpm-channel-name = "rpm_requests";
+ rpm-standalone;
+ };
+
+ qcom,smdpkt {
+ compatible = "qcom,smdpkt";
+
+ qcom,smdpkt-apr-apps2 {
+ qcom,smdpkt-remote = "adsp";
+ qcom,smdpkt-port-name = "apr_apps2";
+ qcom,smdpkt-dev-name = "apr_apps2";
+ };
+
+ qcom,smdpkt-loopback {
+ qcom,smdpkt-remote = "modem";
+ qcom,smdpkt-port-name = "LOOPBACK";
+ qcom,smdpkt-dev-name = "smd_pkt_loopback";
+ };
+ };
+
+ glink_mpss: qcom,glink-ssr-modem {
+ compatible = "qcom,glink_ssr";
+ label = "modem";
+ qcom,edge = "mpss";
+ qcom,notify-edges = <&glink_lpass>, <&glink_dsps>, <&glink_rpm>,
+ <&glink_spss>;
+ qcom,xprt = "smem";
+ };
+
+ glink_lpass: qcom,glink-ssr-adsp {
+ compatible = "qcom,glink_ssr";
+ label = "adsp";
+ qcom,edge = "lpass";
+ qcom,notify-edges = <&glink_mpss>, <&glink_dsps>, <&glink_rpm>,
+ <&glink_spss>;
+ qcom,xprt = "smem";
+ };
+
+ glink_dsps: qcom,glink-ssr-dsps {
+ compatible = "qcom,glink_ssr";
+ label = "slpi";
+ qcom,edge = "dsps";
+ qcom,notify-edges = <&glink_mpss>, <&glink_lpass>, <&glink_rpm>,
+ <&glink_spss>;
+ qcom,xprt = "smem";
+ };
+
+ glink_rpm: qcom,glink-ssr-rpm {
+ compatible = "qcom,glink_ssr";
+ label = "rpm";
+ qcom,edge = "rpm";
+ qcom,notify-edges = <&glink_lpass>, <&glink_mpss>,
+ <&glink_dsps>, <&glink_spss>;
+ qcom,xprt = "smem";
+ };
+
+ glink_spss: qcom,glink-ssr-spss {
+ compatible = "qcom,glink_ssr";
+ label = "spss";
+ qcom,edge = "spss";
+ qcom,notify-edges = <&glink_mpss>, <&glink_lpass>,
+ <&glink_dsps>, <&glink_rpm>;
+ qcom,xprt = "mailbox";
+ };
+
+ qcom,glink-smem-native-xprt-modem@86000000 {
+ compatible = "qcom,glink-smem-native-xprt";
+ reg = <0x86000000 0x200000>,
+ <0x17911008 0x4>;
+ reg-names = "smem", "irq-reg-base";
+ qcom,irq-mask = <0x8000>;
+ interrupts = <0 452 1>;
+ label = "mpss";
+ };
+
+ qcom,glink-smem-native-xprt-adsp@86000000 {
+ compatible = "qcom,glink-smem-native-xprt";
+ reg = <0x86000000 0x200000>,
+ <0x17911008 0x4>;
+ reg-names = "smem", "irq-reg-base";
+ qcom,irq-mask = <0x200>;
+ interrupts = <0 157 1>;
+ label = "lpass";
+ };
+
+ qcom,glink-smem-native-xprt-dsps@86000000 {
+ compatible = "qcom,glink-smem-native-xprt";
+ reg = <0x86000000 0x200000>,
+ <0x17911008 0x4>;
+ reg-names = "smem", "irq-reg-base";
+ qcom,irq-mask = <0x8000000>;
+ interrupts = <0 179 1>;
+ label = "dsps";
+ };
+
+ qcom,glink-smem-native-xprt-rpm@778000 {
+ compatible = "qcom,glink-rpm-native-xprt";
+ reg = <0x778000 0x7000>,
+ <0x17911008 0x4>;
+ reg-names = "msgram", "irq-reg-base";
+ qcom,irq-mask = <0x1>;
+ interrupts = <0 168 1>;
+ label = "rpm";
+ };
+
+ qcom,glink-mailbox-xprt-spss@1d05008 {
+ compatible = "qcom,glink-mailbox-xprt";
+ reg = <0x1d05008 0x8>,
+ <0x1d05010 0x4>,
+ <0x1d0501c 0x4>,
+ <0x1d06008 0x4>;
+ reg-names = "mbox-loc-addr", "mbox-loc-size", "irq-reg-base",
+ "irq-rx-reset";
+ qcom,irq-mask = <0x1>;
+ interrupts = <0 348 4>;
+ label = "spss";
+ qcom,tx-ring-size = <0x800>;
+ qcom,rx-ring-size = <0x800>;
+ };
+
+ qcom,glink_pkt {
+ compatible = "qcom,glinkpkt";
+
+ qcom,glinkpkt-at-mdm0 {
+ qcom,glinkpkt-transport = "smd_trans";
+ qcom,glinkpkt-edge = "mpss";
+ qcom,glinkpkt-ch-name = "DS";
+ qcom,glinkpkt-dev-name = "at_mdm0";
+ };
+
+ qcom,glinkpkt-loopback_cntl {
+ qcom,glinkpkt-transport = "lloop";
+ qcom,glinkpkt-edge = "local";
+ qcom,glinkpkt-ch-name = "LOCAL_LOOPBACK_CLNT";
+ qcom,glinkpkt-dev-name = "glink_pkt_loopback_ctrl";
+ };
+
+ qcom,glinkpkt-loopback_data {
+ qcom,glinkpkt-transport = "lloop";
+ qcom,glinkpkt-edge = "local";
+ qcom,glinkpkt-ch-name = "glink_pkt_lloop_CLNT";
+ qcom,glinkpkt-dev-name = "glink_pkt_loopback";
+ };
+ };
+
+ qcom,ipc_router {
+ compatible = "qcom,ipc_router";
+ qcom,node-id = <1>;
+ };
+
+ qcom,ipc_router_modem_xprt {
+ compatible = "qcom,ipc_router_glink_xprt";
+ qcom,ch-name = "IPCRTR";
+ qcom,xprt-remote = "mpss";
+ qcom,glink-xprt = "smem";
+ qcom,xprt-linkid = <1>;
+ qcom,xprt-version = <1>;
+ qcom,fragmented-data;
+ };
+
+ qcom,ipc_router_q6_xprt {
+ compatible = "qcom,ipc_router_glink_xprt";
+ qcom,ch-name = "IPCRTR";
+ qcom,xprt-remote = "lpass";
+ qcom,glink-xprt = "smem";
+ qcom,xprt-linkid = <1>;
+ qcom,xprt-version = <1>;
+ qcom,fragmented-data;
+ };
+
+ qcom,ipc_router_dsps_xprt {
+ compatible = "qcom,ipc_router_glink_xprt";
+ qcom,ch-name = "IPCRTR";
+ qcom,xprt-remote = "dsps";
+ qcom,glink-xprt = "smem";
+ qcom,xprt-linkid = <1>;
+ qcom,xprt-version = <1>;
+ qcom,fragmented-data;
+ };
+
+ qcom,spcom {
+ compatible = "qcom,spcom";
+
+ /* predefined channels, remote side is server */
+ qcom,spcom-ch-names = "sp_kernel" , "sp_ssr";
+ status = "ok";
+ };
+
+ sdhc_2: sdhci@c0a4900 {
+ compatible = "qcom,sdhci-msm";
+ reg = <0xc0a4900 0x314>, <0xc0a4000 0x800>;
+ reg-names = "hc_mem", "core_mem";
+
+ interrupts = <0 125 0>, <0 221 0>;
+ interrupt-names = "hc_irq", "pwr_irq";
+
+ clock-names = "iface_clk", "core_clk";
+ clocks = <&clock_gcc clk_gcc_sdcc2_ahb_clk>,
+ <&clock_gcc clk_gcc_sdcc2_apps_clk>;
+
+ qcom,large-address-bus;
+ qcom,bus-width = <4>;
+ qcom,cpu-dma-latency-us = <701>;
+
+ qcom,devfreq,freq-table = <52000000 200000000>;
+
+ qcom,msm-bus,name = "sdhc2";
+ qcom,msm-bus,num-cases = <8>;
+ qcom,msm-bus,num-paths = <1>;
+ qcom,msm-bus,vectors-KBps = <81 512 0 0>, /* No vote */
+ <81 512 1600 3200>, /* 400 KB/s*/
+ <81 512 80000 160000>, /* 20 MB/s */
+ <81 512 100000 200000>, /* 25 MB/s */
+ <81 512 200000 400000>, /* 50 MB/s */
+ <81 512 400000 800000>, /* 100 MB/s */
+ <81 512 800000 800000>, /* 200 MB/s */
+ <81 512 2048000 4096000>; /* Max. bandwidth */
+ qcom,bus-bw-vectors-bps = <0 400000 20000000 25000000 50000000
+ 100000000 200000000 4294967295>;
+
+ status = "disabled";
+ };
+
+ ufsphy1: ufsphy@1da7000 {
+ compatible = "qcom,ufs-phy-qmp-v3";
+ reg = <0x1da7000 0xda8>;
+ reg-names = "phy_mem";
+ #phy-cells = <0>;
+ vdda-phy-max-microamp = <51430>;
+ vdda-pll-max-microamp = <14170>;
+ vddp-ref-clk-max-microamp = <100>;
+ vddp-ref-clk-always-on;
+ clock-names = "ref_clk_src",
+ "ref_clk";
+ clocks = <&clock_gcc clk_ln_bb_clk1>,
+ <&clock_gcc clk_gcc_ufs_clkref_clk>;
+ status = "disabled";
+ };
+
+ ufs_ice: ufsice@1db0000 {
+ compatible = "qcom,ice";
+ reg = <0x1db0000 0x8000>;
+ qcom,enable-ice-clk;
+ clock-names = "ufs_core_clk_src",
+ "ufs_core_clk",
+ "bus_clk",
+ "iface_clk",
+ "ice_core_clk_src",
+ "ice_core_clk";
+ clocks = <&clock_gcc clk_ufs_axi_clk_src>,
+ <&clock_gcc clk_gcc_ufs_axi_clk>,
+ <&clock_gcc clk_gcc_aggre1_ufs_axi_clk>,
+ <&clock_gcc clk_gcc_ufs_ahb_clk>,
+ <&clock_gcc clk_ufs_ice_core_clk_src>,
+ <&clock_gcc clk_gcc_ufs_ice_core_clk>;
+ qcom,op-freq-hz = <0>,
+ <0>,
+ <0>,
+ <0>,
+ <300000000>,
+ <0>;
+ vdd-hba-supply = <&gdsc_ufs>;
+ qcom,msm-bus,name = "ufs_ice_noc";
+ qcom,msm-bus,num-cases = <2>;
+ qcom,msm-bus,num-paths = <1>;
+ qcom,msm-bus,vectors-KBps =
+ <1 650 0 0>, /* No vote */
+ <1 650 1000 0>; /* Max. bandwidth */
+ qcom,bus-vector-names = "MIN",
+ "MAX";
+ qcom,instance-type = "ufs";
+ status = "disabled";
+ };
+
+ ufs1: ufshc@1da4000 {
+ compatible = "jedec,ufs-1.1";
+ reg = <0x1da4000 0x2500>;
+ interrupts = <0 265 0>;
+ phys = <&ufsphy1>;
+ phy-names = "ufsphy";
+ vdd-hba-supply = <&gdsc_ufs>;
+ vdd-hba-fixed-regulator;
+ vcc-max-microamp = <750000>;
+ vccq-max-microamp = <450000>;
+ vccq2-max-microamp = <750000>;
+ ufs-qcom-crypto = <&ufs_ice>;
+
+ clock-names =
+ "core_clk_src",
+ "core_clk",
+ "bus_aggr_clk",
+ "iface_clk",
+ "core_clk_unipro_src",
+ "core_clk_unipro",
+ "core_clk_ice",
+ "ref_clk",
+ "tx_lane0_sync_clk",
+ "rx_lane0_sync_clk";
+ clocks =
+ <&clock_gcc clk_ufs_axi_clk_src>,
+ <&clock_gcc clk_gcc_ufs_axi_clk>,
+ <&clock_gcc clk_gcc_aggre1_ufs_axi_clk>,
+ <&clock_gcc clk_gcc_ufs_ahb_clk>,
+ <&clock_gcc clk_ufs_ice_core_clk_src>,
+ <&clock_gcc clk_gcc_ufs_unipro_core_clk>,
+ <&clock_gcc clk_gcc_ufs_ice_core_clk>,
+ <&clock_gcc clk_ln_bb_clk1>,
+ <&clock_gcc clk_gcc_ufs_tx_symbol_0_clk>,
+ <&clock_gcc clk_gcc_ufs_rx_symbol_0_clk>;
+ freq-table-hz =
+ <100000000 200000000>,
+ <0 0>,
+ <0 0>,
+ <0 0>,
+ <150000000 300000000>,
+ <0 0>,
+ <0 0>,
+ <0 0>,
+ <0 0>,
+ <0 0>;
+
+ lanes-per-direction = <1>;
+ qcom,msm-bus,name = "ufs1";
+ qcom,msm-bus,num-cases = <12>;
+ qcom,msm-bus,num-paths = <2>;
+ qcom,msm-bus,vectors-KBps =
+ <95 512 0 0>, <1 650 0 0>, /* No vote */
+ <95 512 922 0>, <1 650 1000 0>, /* PWM G1 */
+ <95 512 1844 0>, <1 650 1000 0>, /* PWM G2 */
+ <95 512 3688 0>, <1 650 1000 0>, /* PWM G3 */
+ <95 512 7376 0>, <1 650 1000 0>, /* PWM G4 */
+ <95 512 127796 0>, <1 650 1000 0>, /* HS G1 RA */
+ <95 512 255591 0>, <1 650 1000 0>, /* HS G2 RA */
+ <95 512 511181 0>, <1 650 1000 0>, /* HS G3 RA */
+ <95 512 149422 0>, <1 650 1000 0>, /* HS G1 RB */
+ <95 512 298189 0>, <1 650 1000 0>, /* HS G2 RB */
+ <95 512 596378 0>, <1 650 1000 0>, /* HS G3 RB */
+ <95 512 4096000 0>, <1 650 1000 0>; /* Max. bandwidth */
+ qcom,bus-vector-names = "MIN",
+ "PWM_G1_L1", "PWM_G2_L1", "PWM_G3_L1", "PWM_G4_L1",
+ "HS_RA_G1_L1", "HS_RA_G2_L1", "HS_RA_G3_L1",
+ "HS_RB_G1_L1", "HS_RB_G2_L1", "HS_RB_G3_L1",
+ "MAX";
+
+ qcom,cpu-affinity = "affine_cores";
+ qcom,cpu-dma-latency-us = <301>;
+
+ status = "disabled";
+
+ ufs_variant {
+ compatible = "qcom,ufs_variant";
+ };
+ };
+
+ usb3: ssusb@a800000 {
+ compatible = "qcom,dwc-usb3-msm";
+ reg = <0x0a800000 0xf8c00>,
+ <0x0c016000 0x400>;
+ reg-names = "core_base", "ahb2phy_base";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ interrupts = <0 133 0>, <0 180 0>;
+ interrupt-names = "hs_phy_irq", "pwr_event_irq";
+
+ USB3_GDSC-supply = <&gdsc_usb30>;
+ qcom,msm-bus,name = "usb3";
+ qcom,msm-bus,num-cases = <2>;
+ qcom,msm-bus,num-paths = <1>;
+ qcom,msm-bus,vectors-KBps =
+ <61 512 0 0>,
+ <61 512 240000 960000>;
+
+ qcom,dwc-usb3-msm-tx-fifo-size = <21288>;
+
+ clocks = <&clock_gcc clk_gcc_usb30_master_clk>,
+ <&clock_gcc clk_gcc_cfg_noc_usb3_axi_clk>,
+ <&clock_gcc clk_gcc_aggre1_usb3_axi_clk>,
+ <&clock_gcc clk_gcc_usb30_mock_utmi_clk>,
+ <&clock_gcc clk_gcc_usb30_sleep_clk>,
+ <&clock_gcc clk_gcc_usb_phy_cfg_ahb2phy_clk>,
+ <&clock_gcc clk_cxo_dwc3_clk>;
+
+ clock-names = "core_clk", "iface_clk", "bus_aggr_clk",
+ "utmi_clk", "sleep_clk", "cfg_ahb_clk", "xo";
+
+ dwc3@a800000 {
+ compatible = "snps,dwc3";
+ reg = <0x0a800000 0xcd00>;
+ interrupt-parent = <&intc>;
+ interrupts = <0 131 0>;
+ usb-phy = <&qusb_phy0>, <&ssphy>;
+ tx-fifo-resize;
+ snps,usb3-u1u2-disable;
+ snps,nominal-elastic-buffer;
+ snps,hird_thresh = <0x10>;
+ };
+ };
+
+ android_usb {
+ compatible = "qcom,android-usb";
+ };
+
+ qusb_phy0: qusb@c012200 {
+ compatible = "qcom,qusb2phy";
+ reg = <0x0c012200 0xb0>,
+ <0x0a8f8800 0x400>,
+ <0x0078024c 0x4>;
+ reg-names = "qusb_phy_base",
+ "qscratch_base",
+ "tune2_efuse_addr";
+ vdd-supply = <&pmcobalt_l1>;
+ vdda18-supply = <&pmcobalt_l12>;
+ vdda33-supply = <&pmcobalt_l24>;
+ qcom,vdd-voltage-level = <0 880000 880000>;
+ phy_type= "utmi";
+
+ clocks = <&clock_gcc clk_ln_bb_clk1>,
+ <&clock_gcc clk_gcc_rx1_usb2_clkref_clk>,
+ <&clock_gcc clk_gcc_usb_phy_cfg_ahb2phy_clk>,
+ <&clock_gcc clk_gcc_qusb2phy_prim_reset>;
+
+ clock-names = "ref_clk_src", "ref_clk", "cfg_ahb_clk",
+ "phy_reset";
+ };
+
+ ssphy: ssphy@c010000 {
+ compatible = "qcom,usb-ssphy-qmp-v2";
+ reg = <0x0c010000 0xbf8>,
+ <0x01fcb244 0x4>;
+ reg-names = "qmp_phy_base",
+ "vls_clamp_reg";
+ vdd-supply = <&pmcobalt_l1>;
+ vdda18-supply = <&pmcobalt_l12>;
+ qcom,vdd-voltage-level = <0 880000 880000>;
+ qcom,vbus-valid-override;
+
+ clocks = <&clock_gcc clk_gcc_usb3_phy_aux_clk>,
+ <&clock_gcc clk_gcc_usb3_phy_pipe_clk>,
+ <&clock_gcc clk_gcc_usb_phy_cfg_ahb2phy_clk>,
+ <&clock_gcc clk_gcc_usb3_phy_reset>,
+ <&clock_gcc clk_gcc_usb3phy_phy_reset>,
+ <&clock_gcc clk_ln_bb_clk1>,
+ <&clock_gcc clk_gcc_usb3_clkref_clk>;
+
+ clock-names = "aux_clk", "pipe_clk", "cfg_ahb_clk", "phy_reset",
+ "phy_phy_reset", "ref_clk_src", "ref_clk";
+ };
+
+ qcom,lpass@17300000 {
+ compatible = "qcom,pil-tz-generic";
+ reg = <0x17300000 0x00100>;
+ interrupts = <0 162 1>;
+
+ vdd_cx-supply = <&pmcobalt_s1_level>;
+ qcom,proxy-reg-names = "vdd_cx";
+ qcom,vdd_cx-uV-uA = <RPM_SMD_REGULATOR_LEVEL_TURBO 100000>;
+
+ clocks = <&clock_gcc clk_cxo_pil_lpass_clk>;
+ clock-names = "xo";
+ qcom,proxy-clock-names = "xo";
+
+ qcom,pas-id = <1>;
+ qcom,proxy-timeout-ms = <10000>;
+ qcom,smem-id = <423>;
+ qcom,sysmon-id = <1>;
+ qcom,ssctl-instance-id = <0x14>;
+ qcom,firmware-name = "adsp";
+ memory-region = <&peripheral_mem>;
+
+ /* GPIO inputs from lpass */
+ qcom,gpio-err-fatal = <&smp2pgpio_ssr_smp2p_2_in 0 0>;
+ qcom,gpio-proxy-unvote = <&smp2pgpio_ssr_smp2p_2_in 2 0>;
+ qcom,gpio-err-ready = <&smp2pgpio_ssr_smp2p_2_in 1 0>;
+ qcom,gpio-stop-ack = <&smp2pgpio_ssr_smp2p_2_in 3 0>;
+
+ /* GPIO output to lpass */
+ qcom,gpio-force-stop = <&smp2pgpio_ssr_smp2p_2_out 0 0>;
+ };
+
+ pil_modem: qcom,mss@4080000 {
+ compatible = "qcom,pil-q6v55-mss";
+ reg = <0x4080000 0x100>,
+ <0x1f63000 0x008>,
+ <0x1f65000 0x008>,
+ <0x1f64000 0x008>,
+ <0x4180000 0x020>,
+ <0x00179000 0x004>;
+ reg-names = "qdsp6_base", "halt_q6", "halt_modem",
+ "halt_nc", "rmb_base", "restart_reg";
+
+ clocks = <&clock_gcc clk_cxo_clk_src>,
+ <&clock_gcc clk_gcc_mss_cfg_ahb_clk>,
+ <&clock_gcc clk_pnoc_clk>,
+ <&clock_gcc clk_gcc_mss_q6_bimc_axi_clk>,
+ <&clock_gcc clk_gcc_boot_rom_ahb_clk>,
+ <&clock_gcc clk_gpll0_out_msscc>,
+ <&clock_gcc clk_gcc_mss_snoc_axi_clk>,
+ <&clock_gcc clk_gcc_mss_mnoc_bimc_axi_clk>,
+ <&clock_gcc clk_qdss_clk>;
+ clock-names = "xo", "iface_clk", "pnoc_clk", "bus_clk",
+ "mem_clk", "gpll0_mss_clk", "snoc_axi_clk",
+ "mnoc_axi_clk", "qdss_clk";
+ qcom,proxy-clock-names = "xo", "pnoc_clk", "qdss_clk";
+ qcom,active-clock-names = "iface_clk", "bus_clk", "mem_clk",
+ "gpll0_mss_clk", "snoc_axi_clk",
+ "mnoc_axi_clk";
+
+ interrupts = <0 448 1>;
+ vdd_cx-supply = <&pmcobalt_s1_level>;
+ vdd_cx-voltage = <RPM_SMD_REGULATOR_LEVEL_TURBO>;
+ vdd_mx-supply = <&pmcobalt_s9_level>;
+ vdd_mx-uV = <RPM_SMD_REGULATOR_LEVEL_TURBO>;
+ vdd_pll-supply = <&pm8005_s3>;
+ qcom,vdd_pll = <600000>;
+ qcom,firmware-name = "modem";
+ qcom,pil-self-auth;
+ qcom,sysmon-id = <0>;
+ qcom,ssctl-instance-id = <0x12>;
+ qcom,override-acc;
+ qcom,qdsp6v62-1-2;
+ memory-region = <&modem_mem>;
+ qcom,mem-protect-id = <0xF>;
+
+ /* GPIO inputs from mss */
+ qcom,gpio-err-fatal = <&smp2pgpio_ssr_smp2p_1_in 0 0>;
+ qcom,gpio-err-ready = <&smp2pgpio_ssr_smp2p_1_in 1 0>;
+ qcom,gpio-proxy-unvote = <&smp2pgpio_ssr_smp2p_1_in 2 0>;
+ qcom,gpio-stop-ack = <&smp2pgpio_ssr_smp2p_1_in 3 0>;
+ qcom,gpio-shutdown-ack = <&smp2pgpio_ssr_smp2p_1_in 7 0>;
+
+ /* GPIO output to mss */
+ qcom,gpio-force-stop = <&smp2pgpio_ssr_smp2p_1_out 0 0>;
+ };
+
+ tsens0: tsens@10aa000 {
+ compatible = "qcom,msmcobalt-tsens";
+ reg = <0x10aa000 0x2000>,
+ <0x74230 0x1000>;
+ reg-names = "tsens_physical", "tsens_eeprom_physical";
+ interrupts = <0 458 0>, <0 445 0>;
+ interrupt-names = "tsens-upper-lower", "tsens-critical";
+ qcom,sensors = <14>;
+ qcom,slope = <2901 2846 3200 3200 3200 3200 3200 3200 3200
+ 3200 3200 3200 3200 3200>;
+ };
+
+ tsens1: tsens@10ad000 {
+ compatible = "qcom,msmcobalt-tsens";
+ reg = <0x10ad000 0x2000>,
+ <0x75230 0x1000>;
+ reg-names = "tsens_physical", "tsens_eeprom_physical";
+ interrupts = <0 184 0>, <0 430 0>;
+ interrupt-names = "tsens-upper-lower", "tsens-critical";
+ qcom,client-id = <14 15 16 17 18 19 20 21>;
+ qcom,sensor-id = <0 1 3 4 5 6 7 2>;
+ qcom,sensors = <8>;
+ qcom,slope = <2901 2846 3200 3200 3200 3200 3200 3200>;
+ };
+
+ qcom,sensor-information {
+ compatible = "qcom,sensor-information";
+ sensor_information0: qcom,sensor-information-0 {
+ qcom,sensor-type = "tsens";
+ qcom,sensor-name = "tsens_tz_sensor0";
+ qcom,scaling-factor = <10>;
+ };
+ sensor_information1: qcom,sensor-information-1 {
+ qcom,sensor-type = "tsens";
+ qcom,sensor-name = "tsens_tz_sensor1";
+ qcom,alias-name = "pop_mem";
+ qcom,scaling-factor = <10>;
+ };
+ sensor_information2: qcom,sensor-information-2 {
+ qcom,sensor-type = "tsens";
+ qcom,sensor-name = "tsens_tz_sensor2";
+ qcom,scaling-factor = <10>;
+ };
+ sensor_information3: qcom,sensor-information-3 {
+ qcom,sensor-type = "tsens";
+ qcom,sensor-name = "tsens_tz_sensor3";
+ qcom,scaling-factor = <10>;
+ };
+ sensor_information4: qcom,sensor-information-4 {
+ qcom,sensor-type = "tsens";
+ qcom,sensor-name = "tsens_tz_sensor4";
+ qcom,scaling-factor = <10>;
+ };
+ sensor_information5: qcom,sensor-information-5 {
+ qcom,sensor-type = "tsens";
+ qcom,sensor-name = "tsens_tz_sensor5";
+ qcom,scaling-factor = <10>;
+ };
+ sensor_information6: qcom,sensor-information-6 {
+ qcom,sensor-type = "tsens";
+ qcom,sensor-name = "tsens_tz_sensor6";
+ qcom,scaling-factor = <10>;
+ };
+ sensor_information7: qcom,sensor-information-7 {
+ qcom,sensor-type = "tsens";
+ qcom,sensor-name = "tsens_tz_sensor7";
+ qcom,scaling-factor = <10>;
+ };
+ sensor_information8: qcom,sensor-information-8 {
+ qcom,sensor-type = "tsens";
+ qcom,sensor-name = "tsens_tz_sensor8";
+ qcom,scaling-factor = <10>;
+ };
+ sensor_information9: qcom,sensor-information-9 {
+ qcom,sensor-type = "tsens";
+ qcom,sensor-name = "tsens_tz_sensor9";
+ qcom,scaling-factor = <10>;
+ };
+ sensor_information10: qcom,sensor-information-10 {
+ qcom,sensor-type = "tsens";
+ qcom,sensor-name = "tsens_tz_sensor10";
+ qcom,scaling-factor = <10>;
+ };
+ sensor_information11: qcom,sensor-information-11 {
+ qcom,sensor-type = "tsens";
+ qcom,sensor-name = "tsens_tz_sensor11";
+ qcom,scaling-factor = <10>;
+ };
+ sensor_information12: qcom,sensor-information-12 {
+ qcom,sensor-type = "tsens";
+ qcom,sensor-name = "tsens_tz_sensor12";
+ qcom,scaling-factor = <10>;
+ };
+ sensor_information13: qcom,sensor-information-13 {
+ qcom,sensor-type = "tsens";
+ qcom,sensor-name = "tsens_tz_sensor13";
+ qcom,scaling-factor = <10>;
+ };
+ sensor_information14: qcom,sensor-information-14 {
+ qcom,sensor-type = "tsens";
+ qcom,sensor-name = "tsens_tz_sensor14";
+ qcom,scaling-factor = <10>;
+ };
+ sensor_information15: qcom,sensor-information-15 {
+ qcom,sensor-type = "tsens";
+ qcom,sensor-name = "tsens_tz_sensor15";
+ qcom,alias-name = "gpu";
+ qcom,scaling-factor = <10>;
+ };
+ sensor_information16: qcom,sensor-information-16 {
+ qcom,sensor-type = "tsens";
+ qcom,sensor-name = "tsens_tz_sensor16";
+ qcom,alias-name = "pop_mem";
+ qcom,scaling-factor = <10>;
+ };
+ sensor_information17: qcom,sensor-information-17 {
+ qcom,sensor-type = "tsens";
+ qcom,sensor-name = "tsens_tz_sensor17";
+ qcom,scaling-factor = <10>;
+ };
+ sensor_information18: qcom,sensor-information-18 {
+ qcom,sensor-type = "tsens";
+ qcom,sensor-name = "tsens_tz_sensor18";
+ qcom,scaling-factor = <10>;
+ };
+ sensor_information19: qcom,sensor-information-19 {
+ qcom,sensor-type = "tsens";
+ qcom,sensor-name = "tsens_tz_sensor19";
+ qcom,scaling-factor = <10>;
+ };
+ sensor_information20: qcom,sensor-information-20 {
+ qcom,sensor-type = "tsens";
+ qcom,sensor-name = "tsens_tz_sensor20";
+ qcom,scaling-factor = <10>;
+ };
+ sensor_information21: qcom,sensor-information-21 {
+ qcom,sensor-type = "tsens";
+ qcom,sensor-name = "tsens_tz_sensor21";
+ qcom,scaling-factor = <10>;
+ };
+ sensor_information22: qcom,sensor-information-22 {
+ qcom,sensor-type = "alarm";
+ qcom,sensor-name = "pm8994_tz";
+ qcom,scaling-factor = <1000>;
+ };
+ sensor_information23: qcom,sensor-information-23 {
+ qcom,sensor-type = "adc";
+ qcom,sensor-name = "msm_therm";
+ };
+ sensor_information24: qcom,sensor-information-24 {
+ qcom,sensor-type = "adc";
+ qcom,sensor-name = "emmc_therm";
+ };
+ sensor_information25: qcom,sensor-information-25 {
+ qcom,sensor-type = "adc";
+ qcom,sensor-name = "pa_therm0";
+ };
+ sensor_information26: qcom,sensor-information-26 {
+ qcom,sensor-type = "adc";
+ qcom,sensor-name = "pa_therm1";
+ };
+ sensor_information27: qcom,sensor-information-27 {
+ qcom,sensor-type = "adc";
+ qcom,sensor-name = "quiet_therm";
+ };
+ };
+
+ mitigation_profile0: qcom,limit_info-0 {
+ qcom,temperature-sensor = <&sensor_information1>;
+ qcom,boot-frequency-mitigate;
+ qcom,hotplug-mitigation-enable;
+ };
+
+ mitigation_profile1: qcom,limit_info-1 {
+ qcom,temperature-sensor = <&sensor_information2>;
+ qcom,boot-frequency-mitigate;
+ qcom,hotplug-mitigation-enable;
+ };
+
+ mitigation_profile2: qcom,limit_info-2 {
+ qcom,temperature-sensor = <&sensor_information3>;
+ qcom,boot-frequency-mitigate;
+ qcom,hotplug-mitigation-enable;
+ };
+
+ mitigation_profile3: qcom,limit_info-3 {
+ qcom,temperature-sensor = <&sensor_information4>;
+ qcom,boot-frequency-mitigate;
+ qcom,hotplug-mitigation-enable;
+ };
+
+ mitigation_profile4: qcom,limit_info-4 {
+ qcom,temperature-sensor = <&sensor_information7>;
+ qcom,boot-frequency-mitigate;
+ qcom,hotplug-mitigation-enable;
+ };
+
+ mitigation_profile5: qcom,limit_info-5 {
+ qcom,temperature-sensor = <&sensor_information8>;
+ qcom,boot-frequency-mitigate;
+ qcom,hotplug-mitigation-enable;
+ };
+
+ mitigation_profile6: qcom,limit_info-6 {
+ qcom,temperature-sensor = <&sensor_information9>;
+ qcom,boot-frequency-mitigate;
+ qcom,hotplug-mitigation-enable;
+ };
+
+ mitigation_profile7: qcom,limit_info-7 {
+ qcom,temperature-sensor = <&sensor_information10>;
+ qcom,boot-frequency-mitigate;
+ qcom,hotplug-mitigation-enable;
+ };
+
+ qcom,msm-thermal {
+ compatible = "qcom,msm-thermal";
+ qcom,sensor-id = <1>;
+ qcom,poll-ms = <100>;
+ qcom,limit-temp = <60>;
+ qcom,temp-hysteresis = <10>;
+ qcom,therm-reset-temp = <115>;
+ qcom,freq-step = <4>;
+ qcom,core-limit-temp = <70>;
+ qcom,core-temp-hysteresis = <10>;
+ qcom,hotplug-temp = <70>;
+ qcom,hotplug-temp-hysteresis = <20>;
+ qcom,online-hotplug-core;
+ qcom,synchronous-cluster-id = <0 1>;
+ qcom,synchronous-cluster-map = <0 4 &CPU0 &CPU1 &CPU2 &CPU3>,
+ <1 4 &CPU4 &CPU5 &CPU6 &CPU7>;
+ };
+
+ qcom,ssc@5c00000 {
+ compatible = "qcom,pil-tz-generic";
+ reg = <0x5c00000 0x4000>;
+ interrupts = <0 390 1>;
+
+ vdd_cx-supply = <&pmcobalt_l27_level>;
+ vdd_px-supply = <&pmcobalt_lvs2>;
+ qcom,vdd_cx-uV-uA = <RPM_SMD_REGULATOR_LEVEL_TURBO 0>;
+ qcom,proxy-reg-names = "vdd_cx", "vdd_px";
+ qcom,keep-proxy-regs-on;
+
+ clocks = <&clock_gcc clk_cxo_pil_ssc_clk>,
+ <&clock_gcc clk_aggre2_noc_clk>;
+ clock-names = "xo", "aggre2";
+ qcom,proxy-clock-names = "xo", "aggre2";
+
+ qcom,pas-id = <12>;
+ qcom,proxy-timeout-ms = <10000>;
+ qcom,smem-id = <424>;
+ qcom,sysmon-id = <3>;
+ qcom,ssctl-instance-id = <0x16>;
+ qcom,firmware-name = "slpi";
+ memory-region = <&peripheral_mem>;
+
+ /* GPIO inputs from ssc */
+ qcom,gpio-err-fatal = <&smp2pgpio_ssr_smp2p_3_in 0 0>;
+ qcom,gpio-proxy-unvote = <&smp2pgpio_ssr_smp2p_3_in 2 0>;
+ qcom,gpio-err-ready = <&smp2pgpio_ssr_smp2p_3_in 1 0>;
+ qcom,gpio-stop-ack = <&smp2pgpio_ssr_smp2p_3_in 3 0>;
+
+ /* GPIO output to ssc */
+ qcom,gpio-force-stop = <&smp2pgpio_ssr_smp2p_3_out 0 0>;
+ };
+
+ qcom,venus@cce0000 {
+ compatible = "qcom,pil-tz-generic";
+ reg = <0xcce0000 0x4000>;
+
+ vdd-supply = <&gdsc_venus>;
+ qcom,proxy-reg-names = "vdd";
+
+ clocks = <&clock_mmss clk_mmss_video_core_clk>,
+ <&clock_mmss clk_mmss_video_ahb_clk>,
+ <&clock_mmss clk_mmss_video_axi_clk>,
+ <&clock_mmss clk_mmss_video_maxi_clk>;
+ clock-names = "core_clk", "iface_clk",
+ "bus_clk", "maxi_clk";
+ qcom,proxy-clock-names = "core_clk", "iface_clk",
+ "bus_clk", "maxi_clk";
+
+ qcom,pas-id = <9>;
+ qcom,proxy-timeout-ms = <100>;
+ qcom,firmware-name = "venus";
+ memory-region = <&peripheral_mem>;
+ };
+
+ wdog: qcom,wdt@17817000 {
+ compatible = "qcom,msm-watchdog";
+ reg = <0x17817000 0x1000>;
+ reg-names = "wdt-base";
+ interrupts = <0 3 0>, <0 4 0>;
+ qcom,bark-time = <11000>;
+ qcom,pet-time = <10000>;
+ qcom,ipi-ping;
+ qcom,wakeup-enable;
+ };
+
+ qcom,spss@1d00000 {
+ compatible = "qcom,pil-tz-generic";
+ reg = <0x1d00000 0x20000>;
+ reg-names = "sp_scsr_base";
+ interrupts = <0 352 1>;
+
+ vdd_cx-supply = <&pmcobalt_s1_level>;
+ qcom,proxy-reg-names = "vdd_cx";
+ qcom,vdd_cx-uV-uA = <RPM_SMD_REGULATOR_LEVEL_TURBO 100000>;
+
+ clocks = <&clock_gcc clk_cxo_pil_spss_clk>;
+ clock-names = "xo";
+ qcom,proxy-clock-names = "xo";
+ qcom,pil-generic-irq-handler;
+
+ qcom,pas-id = <14>;
+ qcom,proxy-timeout-ms = <10000>;
+ qcom,firmware-name = "spss";
+ memory-region = <&peripheral_mem>;
+ };
+
+ qcom,msm-rtb {
+ compatible = "qcom,msm-rtb";
+ qcom,rtb-size = <0x100000>;
+ };
+
+ qcom,msm-imem@146bf000 {
+ compatible = "qcom,msm-imem";
+ reg = <0x146bf000 0x1000>;
+ ranges = <0x0 0x146bf000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ mem_dump_table@10 {
+ compatible = "qcom,msm-imem-mem_dump_table";
+ reg = <0x10 8>;
+ };
+
+ restart_reason@65c {
+ compatible = "qcom,msm-imem-restart_reason";
+ reg = <0x65c 4>;
+ };
+
+ boot_stats@6b0 {
+ compatible = "qcom,msm-imem-boot_stats";
+ reg = <0x6b0 32>;
+ };
+
+ pil@94c {
+ compatible = "qcom,msm-imem-pil";
+ reg = <0x94c 200>;
+ };
+ };
+
+ cpu_pmu: cpu-pmu {
+ compatible = "arm,armv8-pmuv3";
+ qcom,irq-is-percpu;
+ interrupts = <1 6 4>;
+ };
+
+ cpuss_dump {
+ compatible = "qcom,cpuss-dump";
+ qcom,l1_i_cache0 {
+ qcom,dump-node = <&L1_I_0>;
+ qcom,dump-id = <0x60>;
+ };
+ qcom,l1_i_cache1 {
+ qcom,dump-node = <&L1_I_1>;
+ qcom,dump-id = <0x61>;
+ };
+ qcom,l1_i_cache2 {
+ qcom,dump-node = <&L1_I_2>;
+ qcom,dump-id = <0x62>;
+ };
+ qcom,l1_i_cache3 {
+ qcom,dump-node = <&L1_I_3>;
+ qcom,dump-id = <0x63>;
+ };
+ qcom,l1_i_cache100 {
+ qcom,dump-node = <&L1_I_100>;
+ qcom,dump-id = <0x64>;
+ };
+ qcom,l1_i_cache101 {
+ qcom,dump-node = <&L1_I_101>;
+ qcom,dump-id = <0x65>;
+ };
+ qcom,l1_i_cache102 {
+ qcom,dump-node = <&L1_I_102>;
+ qcom,dump-id = <0x66>;
+ };
+ qcom,l1_i_cache103 {
+ qcom,dump-node = <&L1_I_103>;
+ qcom,dump-id = <0x67>;
+ };
+ qcom,l1_d_cache0 {
+ qcom,dump-node = <&L1_D_0>;
+ qcom,dump-id = <0x80>;
+ };
+ qcom,l1_d_cache1 {
+ qcom,dump-node = <&L1_D_1>;
+ qcom,dump-id = <0x81>;
+ };
+ qcom,l1_d_cache2 {
+ qcom,dump-node = <&L1_D_2>;
+ qcom,dump-id = <0x82>;
+ };
+ qcom,l1_d_cache3 {
+ qcom,dump-node = <&L1_D_3>;
+ qcom,dump-id = <0x83>;
+ };
+ qcom,l1_d_cache100 {
+ qcom,dump-node = <&L1_D_100>;
+ qcom,dump-id = <0x84>;
+ };
+ qcom,l1_d_cache101 {
+ qcom,dump-node = <&L1_D_101>;
+ qcom,dump-id = <0x85>;
+ };
+ qcom,l1_d_cache102 {
+ qcom,dump-node = <&L1_D_102>;
+ qcom,dump-id = <0x86>;
+ };
+ qcom,l1_d_cache103 {
+ qcom,dump-node = <&L1_D_103>;
+ qcom,dump-id = <0x87>;
+ };
+ };
+};
+
+&gdsc_mmss {
+ status = "ok";
+};
+
+&gdsc_usb30 {
+ clock-names = "core_clk";
+ clocks = <&clock_gcc clk_gcc_usb30_master_clk>;
+ status = "ok";
+};
+
+&gdsc_pcie_0 {
+ clock-names = "master_bus_clk", "slave_bus_clk", "core_clk";
+ clocks = <&clock_gcc clk_gcc_pcie_0_mstr_axi_clk>,
+ <&clock_gcc clk_gcc_pcie_0_slv_axi_clk>,
+ <&clock_gcc clk_gcc_pcie_0_pipe_clk>;
+ status = "ok";
+};
+
+&gdsc_ufs {
+ clock-names = "bus_clk", "ice_clk", "unipro_clk";
+ clocks = <&clock_gcc clk_gcc_ufs_axi_clk>,
+ <&clock_gcc clk_gcc_ufs_ice_core_clk>,
+ <&clock_gcc clk_gcc_ufs_unipro_core_clk>;
+ status = "ok";
+};
+
+&gdsc_bimc_smmu {
+ clock-names = "bus_clk";
+ clocks = <&clock_mmss clk_mmss_bimc_smmu_axi_clk>;
+ status = "ok";
+};
+
+&gdsc_hlos1_vote_lpass_adsp {
+ status = "ok";
+};
+
+&gdsc_hlos1_vote_lpass_core {
+ status = "ok";
+};
+
+&gdsc_venus {
+ clock-names = "bus_clk", "maxi_clk", "core_clk";
+ clocks = <&clock_mmss clk_mmss_video_axi_clk>,
+ <&clock_mmss clk_mmss_video_maxi_clk>,
+ <&clock_mmss clk_mmss_video_core_clk>;
+ status = "ok";
+};
+
+&gdsc_venus_core0 {
+ clock-names = "core0_clk";
+ clocks = <&clock_mmss clk_mmss_video_subcore0_clk>;
+ status = "ok";
+};
+
+&gdsc_venus_core1 {
+ clock-names = "core1_clk";
+ clocks = <&clock_mmss clk_mmss_video_subcore1_clk>;
+ status = "ok";
+};
+
+&gdsc_camss_top {
+ clock-names = "bus_clk", "vfe_axi";
+ clocks = <&clock_mmss clk_mmss_camss_cpp_axi_clk>,
+ <&clock_mmss clk_mmss_camss_vfe_vbif_axi_clk>;
+ status = "ok";
+};
+
+&gdsc_vfe0 {
+ clock-names = "core0_clk" , "core0_stream_clk";
+ clocks = <&clock_mmss clk_mmss_camss_vfe0_clk>,
+ <&clock_mmss clk_mmss_camss_vfe0_stream_clk>;
+ parent-supply = <&gdsc_camss_top>;
+ status = "ok";
+};
+
+&gdsc_vfe1 {
+ clock-names = "core1_clk" , "core1_stream_clk";
+ clocks = <&clock_mmss clk_mmss_camss_vfe1_clk>,
+ <&clock_mmss clk_mmss_camss_vfe1_stream_clk>;
+ parent-supply = <&gdsc_camss_top>;
+ status = "ok";
+};
+
+&gdsc_cpp {
+ clock-names = "core_clk";
+ clocks = <&clock_mmss clk_mmss_camss_cpp_clk>;
+ parent-supply = <&gdsc_camss_top>;
+ status = "ok";
+};
+
+&gdsc_mdss {
+ clock-names = "bus_clk", "core_clk", "root_clk";
+ clocks = <&clock_mmss clk_mmss_mdss_axi_clk>,
+ <&clock_mmss clk_mmss_mdss_mdp_clk>,
+ <&clock_mmss clk_mmss_mdss_rot_clk>;
+ status = "ok";
+};
+
+&gdsc_gpu_gx {
+ clock-names = "bimc_core_clk", "core_clk", "core_root_clk";
+ clocks = <&clock_gcc clk_gcc_gpu_bimc_gfx_clk>,
+ <&clock_gpu clk_gpucc_gfx3d_clk>,
+ <&clock_gpu clk_gfx3d_clk_src>;
+ qcom,force-enable-root-clk;
+ parent-supply = <&pm8005_s1>;
+ status = "ok";
+};
+
+&gdsc_gpu_cx {
+ status = "ok";
+};
+
+#include "msmcobalt-pm.dtsi"
+#include "msm-arm-smmu-cobalt.dtsi"
+#include "msmcobalt-ion.dtsi"
+#include "msm-pmcobalt-rpm-regulator.dtsi"
+#include "msmcobalt-regulator.dtsi"
+#include "msmcobalt-camera.dtsi"
+#include "msmcobalt-vidc.dtsi"
+#include "msmcobalt-coresight.dtsi"
+#include "msmcobalt-bus.dtsi"
-/* Copyright (c) 2015, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2015-2016, The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
#define clk_gcc_debug_mux 0x8121ac15
/* clock_mmss controlled clocks */
-#define clk_mmpll2 0x1190e4d8
-#define clk_mmpll3 0x18c76899
-#define clk_mmpll4 0x22c063c1
-#define clk_mmpll5 0xa41e1936
-#define clk_mmpll6 0xc56fb440
-#define clk_mmpll7 0x3ac216af
-#define clk_mmpll8 0xd06ad45e
-#define clk_mmpll9 0x1c50684c
-#define clk_mmpll10 0x2561263b
-#define clk_mmpll2_out_main 0x1e9e24a8
-#define clk_mmpll3_out_main 0x6eb6328f
-#define clk_mmpll4_out_main 0xfb21c2fd
-#define clk_mmpll5_out_main 0xcc1897bf
-#define clk_mmpll6_out_main 0xfb1060bd
-#define clk_mmpll7_out_main 0x767758ed
-#define clk_mmpll8_out_main 0x75b1f386
-#define clk_mmpll9_out_main 0x16b74937
-#define clk_mmpll10_out_main 0x3c5668f3
+#define clk_mmsscc_xo 0x05e63704
+#define clk_mmsscc_gpll0 0xe900c515
+#define clk_mmsscc_gpll0_div 0x73892e05
+#define clk_mmpll0_pll 0x361e3cfd
+#define clk_mmpll1_pll 0x198e426b
+#define clk_mmpll3_pll 0x18c76899
+#define clk_mmpll4_pll 0x22c063c1
+#define clk_mmpll5_pll 0xa41e1936
+#define clk_mmpll6_pll 0xc56fb440
+#define clk_mmpll7_pll 0x3ac216af
+#define clk_mmpll10_pll 0x2561263b
+#define clk_mmpll0_pll_out 0x1e9e24a8
+#define clk_mmpll1_pll_out 0x5fa32257
+#define clk_mmpll3_pll_out 0x6eb6328f
+#define clk_mmpll4_pll_out 0xfb21c2fd
+#define clk_mmpll5_pll_out 0xcc1897bf
+#define clk_mmpll6_pll_out 0xfb1060bd
+#define clk_mmpll7_pll_out 0x767758ed
+#define clk_mmpll10_pll_out 0x3c5668f3
+#define clk_ahb_clk_src 0x86f49203
#define clk_csi0_clk_src 0x227e65bc
#define clk_vfe0_clk_src 0xa0c2bd8f
#define clk_vfe1_clk_src 0x4e357366
#define clk_csi2_clk_src 0x4113589f
#define clk_csi3_clk_src 0xfd934012
#define clk_fd_core_clk_src 0xe4799ab7
-#define clk_dp_crypto_clk_src 0xf8faa811
-#define clk_dp_pixel_clk_src 0xf5dfbabf
+#define clk_ext_extpclk_clk_src 0xe5b273af
+#define clk_ext_pclk0_clk_src 0x087c1612
+#define clk_ext_pclk1_clk_src 0x8067c5a3
#define clk_pclk0_clk_src 0xccac1f35
#define clk_pclk1_clk_src 0x090f68ac
-#define clk_mmsscc_xo 0x05e63704
-#define clk_mmsscc_gpll0 0xe900c515
#define clk_video_subcore0_clk_src 0x88d79636
#define clk_video_subcore1_clk_src 0x4966930c
#define clk_cci_clk_src 0x822f3d97
#define clk_mclk1_clk_src 0xa73cad0c
#define clk_mclk2_clk_src 0x42545468
#define clk_mclk3_clk_src 0x2bfbb714
+#define clk_csiphy_clk_src 0x8cceb70a
#define clk_csi0phytimer_clk_src 0xc8a309be
#define clk_csi1phytimer_clk_src 0x7c0fe23a
#define clk_csi2phytimer_clk_src 0x62ffea9c
+#define clk_ext_byte0_clk_src 0xfb32f31e
+#define clk_ext_byte1_clk_src 0x585ef6d4
#define clk_byte0_clk_src 0x75cc885b
#define clk_byte1_clk_src 0x63c2c955
#define clk_dp_aux_clk_src 0x2b6e972b
#define clk_dp_gtc_clk_src 0xc5a86a42
-#define clk_dp_link_clk_src 0x370d0626
#define clk_esc0_clk_src 0xb41d7c38
#define clk_esc1_clk_src 0x3b0afa42
#define clk_extpclk_clk_src 0xb2c31abd
#define clk_hdmi_clk_src 0xb40aeea9
#define clk_vsync_clk_src 0xecb43940
-#define clk_bimc_smmu_ahb_clk 0x5b71f87d
-#define clk_bimc_smmu_axi_clk 0x49cfc61c
-#define clk_snoc_dvm_axi_clk 0x72bbd57a
-#define clk_bto_ahb_clk 0x3844ec63
-#define clk_camss_ahb_clk 0xc4ff91d4
-#define clk_camss_cci_ahb_clk 0x04c4441a
-#define clk_camss_cci_clk 0xd6cb5eb9
-#define clk_camss_cpp_ahb_clk 0x12e9a87b
-#define clk_camss_cpp_clk 0xb82f366b
-#define clk_camss_cpp_axi_clk 0x5598c804
-#define clk_camss_cpp_vbif_ahb_clk 0xb5f31be4
-#define clk_camss_cphy_csid0_clk 0x25706297
-#define clk_camss_csi0_ahb_clk 0x6e29c972
-#define clk_camss_csi0_clk 0x30862ddb
-#define clk_camss_csi0pix_clk 0x6946f77b
-#define clk_camss_csi0rdi_clk 0x83645ef5
-#define clk_camss_cphy_csid1_clk 0x0404b393
-#define clk_camss_csi1_ahb_clk 0xccc15f06
-#define clk_camss_csi1_clk 0xb150f052
-#define clk_camss_csi1pix_clk 0x58d19bf3
-#define clk_camss_csi1rdi_clk 0x4d2f3352
-#define clk_camss_cphy_csid2_clk 0xe9d0fe2f
-#define clk_camss_csi2_ahb_clk 0x92d02d75
-#define clk_camss_csi2_clk 0x74fc92e8
-#define clk_camss_csi2pix_clk 0xf8ed0731
-#define clk_camss_csi2rdi_clk 0xdc1b2081
-#define clk_camss_cphy_csid3_clk 0x4eccef6c
-#define clk_camss_csi3_ahb_clk 0xee5e459c
-#define clk_camss_csi3_clk 0x39488fdd
-#define clk_camss_csi3pix_clk 0xd82bd467
-#define clk_camss_csi3rdi_clk 0xb6750046
-#define clk_camss_csi_vfe0_clk 0x3023937a
-#define clk_camss_csi_vfe1_clk 0xe66fa522
-#define clk_camss_csiphy0_clk 0x6e1782f1
-#define clk_camss_csiphy1_clk 0x10d2e851
-#define clk_camss_csiphy2_clk 0x4c54acb5
-#define clk_fd_ahb_clk 0x868a2c5c
-#define clk_fd_core_clk 0x3badcae4
-#define clk_fd_core_uar_clk 0x7e624e15
-#define clk_camss_gp0_clk 0xcee7e51d
-#define clk_camss_gp1_clk 0x41f1c2e3
-#define clk_camss_ispif_ahb_clk 0x9a212c6d
-#define clk_camss_jpeg0_clk 0x0b0e2db7
-#define clk_camss_jpeg_ahb_clk 0x1f47fd28
-#define clk_camss_jpeg_axi_clk 0x9e5545c8
-#define clk_camss_mclk0_clk 0xcf0c61e0
-#define clk_camss_mclk1_clk 0xd1410ed4
-#define clk_camss_mclk2_clk 0x851286f2
-#define clk_camss_mclk3_clk 0x4db11c45
-#define clk_camss_micro_ahb_clk 0x33a23277
-#define clk_camss_csi0phytimer_clk 0xff93b3c8
-#define clk_camss_csi1phytimer_clk 0x6c399ab6
-#define clk_camss_csi2phytimer_clk 0x24f47f49
-#define clk_camss_top_ahb_clk 0x8f8b2d33
-#define clk_camss_vfe0_ahb_clk 0x4652833c
-#define clk_camss_vfe0_clk 0x1e9bb8c4
-#define clk_camss_vfe0_stream_clk 0x22835fa4
-#define clk_camss_vfe1_ahb_clk 0x6a56abd3
-#define clk_camss_vfe1_clk 0x5bffa69b
-#define clk_camss_vfe1_stream_clk 0x92f849b9
-#define clk_camss_vfe_vbif_ahb_clk 0x69b314cf
-#define clk_camss_vfe_vbif_axi_clk 0x37390d57
-#define clk_mdss_ahb_clk 0x684ccb41
-#define clk_mdss_axi_clk 0xcc07d687
-#define clk_mdss_byte0_clk 0xf5a03f64
-#define clk_mdss_byte0_intf_clk 0x78d77f37
-#define clk_mdss_byte1_clk 0xb8c7067d
-#define clk_mdss_byte1_intf_clk 0xca7f2082
-#define clk_mdss_dp_aux_clk 0xac5fd97c
-#define clk_mdss_dp_crypto_clk 0x3492537d
-#define clk_mdss_dp_gtc_clk 0x32341887
-#define clk_mdss_dp_link_clk 0xef31ea17
-#define clk_mdss_dp_link_intf_clk 0x960e00b8
-#define clk_mdss_dp_pixel_clk 0x0173b158
-#define clk_mdss_esc0_clk 0x28cafbe6
-#define clk_mdss_esc1_clk 0xc22c6883
-#define clk_mdss_extpclk_clk 0xfa5aadb0
-#define clk_mdss_hdmi_clk 0x097a6de9
-#define clk_mdss_hdmi_dp_ahb_clk 0x862fc1ba
-#define clk_mdss_mdp_clk 0x618336ac
-#define clk_mdss_pclk0_clk 0x3487234a
-#define clk_mdss_pclk1_clk 0xd5804246
-#define clk_mdss_rot_clk 0x954e31b8
-#define clk_mdss_vsync_clk 0x42a022d3
-#define clk_misc_ahb_clk 0xdfbd704c
-#define clk_misc_cxo_clk 0x012c041f
-#define clk_mnoc_maxi_clk 0x4def770c
-#define clk_spdm_ahb_clk 0xdfae8ed9
-#define clk_spdm_axi_clk 0x31ef53a3
-#define clk_spdm_cpp_clk 0x3f58e5f8
-#define clk_spdm_csi0_clk 0x5e537bc8
-#define clk_spdm_debug_clk 0xa850c7fb
-#define clk_spdm_dp_crypto_clk 0xdb01d21e
-#define clk_spdm_dp_pixel_clk 0x321dd909
-#define clk_spdm_jpeg0_clk 0x28f07f34
-#define clk_spdm_mdp_clk 0xafc15ea1
-#define clk_spdm_pclk0_clk 0x6d440ee3
-#define clk_spdm_pclk1_clk 0xb93af2ab
-#define clk_spdm_rot_clk 0x105c1345
-#define clk_spdm_vfe0_clk 0x64266893
-#define clk_spdm_vfe1_clk 0xdb738e6c
-#define clk_spdm_video_core_clk 0x76baf313
-#define clk_spdm_rm_axi_clk 0x3bac1b23
-#define clk_spdm_rm_maxi_clk 0xd5cf2f39
-#define clk_camss_micro_ahb_slp_stg_clk 0x51441764
-#define clk_throttle_camss_ahb_clk 0x5c3b3b21
-#define clk_throttle_camss_axi_clk 0xbaa23c28
-#define clk_throttle_camss_cxo_clk 0x93e27c3b
-#define clk_throttle_mdss_ahb_clk 0x8ae6585f
-#define clk_throttle_mdss_axi_clk 0xc7850107
-#define clk_throttle_mdss_cxo_clk 0xadb11a10
-#define clk_throttle_video_ahb_clk 0x5612a745
-#define clk_throttle_video_axi_clk 0x06c344d6
-#define clk_throttle_video_cxo_clk 0x808d592e
-#define clk_video_subcore0_clk 0xb6f63e6c
-#define clk_video_subcore1_clk 0x26c29cb4
-#define clk_video_ahb_clk 0x90775cfb
-#define clk_video_axi_clk 0xe6c16dba
-#define clk_video_core_clk 0x7e876ec3
-#define clk_video_maxi_clk 0x97749db6
-#define clk_vmem_ahb_clk 0xab6223ff
-#define clk_vmem_maxi_clk 0x15ef32db
+#define clk_mmss_bimc_smmu_ahb_clk 0x4825baf4
+#define clk_mmss_bimc_smmu_axi_clk 0xc365ac39
+#define clk_mmss_snoc_dvm_axi_clk 0x2c159a11
+#define clk_mmss_camss_ahb_clk 0xa51f2c1d
+#define clk_mmss_camss_cci_ahb_clk 0xfda8bb6a
+#define clk_mmss_camss_cci_clk 0x71bb5c97
+#define clk_mmss_camss_cpp_ahb_clk 0xd5554f15
+#define clk_mmss_camss_cpp_clk 0x8e99ef57
+#define clk_mmss_camss_cpp_axi_clk 0xd84e390b
+#define clk_mmss_camss_cpp_vbif_ahb_clk 0x1b33a88e
+#define clk_mmss_camss_cphy_csid0_clk 0x56114361
+#define clk_mmss_camss_csi0_ahb_clk 0x2b58d241
+#define clk_mmss_camss_csi0_clk 0xccfe39ef
+#define clk_mmss_camss_csi0pix_clk 0x9e26509d
+#define clk_mmss_camss_csi0rdi_clk 0x01d5bf83
+#define clk_mmss_camss_cphy_csid1_clk 0x79fbcd8a
+#define clk_mmss_camss_csi1_ahb_clk 0x7073244b
+#define clk_mmss_camss_csi1_clk 0x3eeeaac0
+#define clk_mmss_camss_csi1pix_clk 0xf1375139
+#define clk_mmss_camss_csi1rdi_clk 0x43185024
+#define clk_mmss_camss_cphy_csid2_clk 0xf295e3ef
+#define clk_mmss_camss_csi2_ahb_clk 0x681c1479
+#define clk_mmss_camss_csi2_clk 0x94524569
+#define clk_mmss_camss_csi2pix_clk 0xf4de617d
+#define clk_mmss_camss_csi2rdi_clk 0x4bf01dc5
+#define clk_mmss_camss_cphy_csid3_clk 0x100188e9
+#define clk_mmss_camss_csi3_ahb_clk 0xfae7c29b
+#define clk_mmss_camss_csi3_clk 0x55e4bbae
+#define clk_mmss_camss_csi3pix_clk 0xc166a015
+#define clk_mmss_camss_csi3rdi_clk 0x6983a4cd
+#define clk_mmss_camss_csi_vfe0_clk 0x3b30b798
+#define clk_mmss_camss_csi_vfe1_clk 0xfe729af7
+#define clk_mmss_camss_csiphy0_clk 0x96c81af8
+#define clk_mmss_camss_csiphy1_clk 0xee9ac2bb
+#define clk_mmss_camss_csiphy2_clk 0x3365e70e
+#define clk_mmss_fd_ahb_clk 0x4ff1da4d
+#define clk_mmss_fd_core_clk 0x749e7eb0
+#define clk_mmss_fd_core_uar_clk 0x8ea480c5
+#define clk_mmss_camss_gp0_clk 0x3f7f6c87
+#define clk_mmss_camss_gp1_clk 0xdccdd730
+#define clk_mmss_camss_ispif_ahb_clk 0xbda4f0e3
+#define clk_mmss_camss_jpeg0_clk 0x4cc73b07
+#define clk_mmss_camss_jpeg_ahb_clk 0xde1fece3
+#define clk_mmss_camss_jpeg_axi_clk 0x7534616b
+#define clk_mmss_camss_mclk0_clk 0x056293a7
+#define clk_mmss_camss_mclk1_clk 0x96c7b69b
+#define clk_mmss_camss_mclk2_clk 0x8820556e
+#define clk_mmss_camss_mclk3_clk 0xf90ffb67
+#define clk_mmss_camss_micro_ahb_clk 0x6c6fd3c7
+#define clk_mmss_camss_csi0phytimer_clk 0x7a78864e
+#define clk_mmss_camss_csi1phytimer_clk 0x6e6c1de5
+#define clk_mmss_camss_csi2phytimer_clk 0x0235e2de
+#define clk_mmss_camss_top_ahb_clk 0x120618d6
+#define clk_mmss_camss_vfe0_ahb_clk 0x137bd0bd
+#define clk_mmss_camss_vfe0_clk 0xead28288
+#define clk_mmss_camss_vfe0_stream_clk 0xa0428287
+#define clk_mmss_camss_vfe1_ahb_clk 0xac0154c0
+#define clk_mmss_camss_vfe1_clk 0xc216b14d
+#define clk_mmss_camss_vfe1_stream_clk 0x745af3b6
+#define clk_mmss_camss_vfe_vbif_ahb_clk 0x0109a9c6
+#define clk_mmss_camss_vfe_vbif_axi_clk 0xe626d8a1
+#define clk_mmss_mdss_ahb_clk 0x85d37ab5
+#define clk_mmss_mdss_axi_clk 0xdf04fc1d
+#define clk_mmss_mdss_byte0_clk 0x38105d25
+#define clk_mmss_mdss_byte1_clk 0xe0c21354
+#define clk_mmss_mdss_dp_aux_clk 0x23125eb6
+#define clk_mmss_mdss_dp_gtc_clk 0xb59c151a
+#define clk_mmss_mdss_esc0_clk 0x5721ff83
+#define clk_mmss_mdss_esc1_clk 0xc3d0376b
+#define clk_mmss_mdss_extpclk_clk 0x74d5a954
+#define clk_mmss_mdss_hdmi_clk 0x28460a6d
+#define clk_mmss_mdss_hdmi_dp_ahb_clk 0x5448519f
+#define clk_mmss_mdss_mdp_clk 0x43539b0e
+#define clk_mmss_mdss_pclk0_clk 0xcc0e909d
+#define clk_mmss_mdss_pclk1_clk 0x850d9146
+#define clk_mmss_mdss_rot_clk 0xbb7e71c4
+#define clk_mmss_mdss_vsync_clk 0x629b36dc
+#define clk_mmss_misc_ahb_clk 0xea30b0e7
+#define clk_mmss_misc_cxo_clk 0xe620cd80
+#define clk_mmss_mnoc_ahb_clk 0x49a394f4
+#define clk_mmss_mnoc_maxi_clk 0xd8b7278f
+#define clk_mmss_throttle_camss_ahb_clk 0x0382ef47
+#define clk_mmss_throttle_camss_axi_clk 0x26271bf4
+#define clk_mmss_throttle_camss_cxo_clk 0xa3d15f10
+#define clk_mmss_throttle_mdss_ahb_clk 0x1ab259f7
+#define clk_mmss_throttle_mdss_axi_clk 0x80067438
+#define clk_mmss_throttle_mdss_cxo_clk 0x8a8daaf7
+#define clk_mmss_throttle_video_ahb_clk 0x9efb223e
+#define clk_mmss_throttle_video_axi_clk 0xe160287c
+#define clk_mmss_throttle_video_cxo_clk 0x7aa7d641
+#define clk_mmss_video_subcore0_clk 0x23fae359
+#define clk_mmss_video_subcore1_clk 0x5213a0c7
+#define clk_mmss_video_ahb_clk 0x94334ae9
+#define clk_mmss_video_axi_clk 0xf3178ba5
+#define clk_mmss_video_core_clk 0x78f14c85
+#define clk_mmss_video_maxi_clk 0x1785ef88
+#define clk_mmss_vmem_ahb_clk 0x4b18955b
+#define clk_mmss_vmem_maxi_clk 0xb6067889
#define clk_mmss_debug_mux 0xe646ffda
/* clock_gpu controlled clocks*/
-/* Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2014-2016, The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
#define MSM_BUS_FAB_A0_NOC 6145
#define MSM_BUS_FAB_A1_NOC 6146
#define MSM_BUS_FAB_A2_NOC 6147
+#define MSM_BUS_FAB_GNOC 6148
+#define MSM_BUS_FAB_CR_VIRT 6149
#define MSM_BUS_MASTER_FIRST 1
#define MSM_BUS_MASTER_AMPSS_M0 1
#define MSM_BUS_MASTER_XI_USB_HSIC 113
#define MSM_BUS_MASTER_SGMII 114
#define MSM_BUS_SPMI_FETCHER 115
-#define MSM_BUS_MASTER_LAST 116
+#define MSM_BUS_MASTER_GNOC_BIMC 116
+#define MSM_BUS_MASTER_CRVIRT_A2NOC 117
+#define MSM_BUS_MASTER_CNOC_A2NOC 118
+#define MSM_BUS_MASTER_WLAN 119
+#define MSM_BUS_MASTER_MSS_CE 120
+#define MSM_BUS_MASTER_MASTER_LAST 121
#define MSM_BUS_SYSTEM_FPB_MASTER_SYSTEM MSM_BUS_SYSTEM_MASTER_SYSTEM_FPB
#define MSM_BUS_CPSS_FPB_MASTER_SYSTEM MSM_BUS_SYSTEM_MASTER_CPSS_FPB
#define MSM_BUS_SLAVE_PCNOC_BIMC_1 718
#define MSM_BUS_SLAVE_SGMII 719
#define MSM_BUS_SLAVE_SPMI_FETCHER 720
-#define MSM_BUS_PNOC_SLV_6 721
-#define MSM_BUS_SLAVE_LAST 722
+#define MSM_BUS_PNOC_SLV_6 721
+#define MSM_BUS_SLAVE_MMSS_SMMU_CFG 722
+#define MSM_BUS_SLAVE_WLAN 723
+#define MSM_BUS_SLAVE_CRVIRT_A2NOC 724
+#define MSM_BUS_SLAVE_CNOC_A2NOC 725
+#define MSM_BUS_SLAVE_GLM 726
+#define MSM_BUS_SLAVE_GNOC_BIMC 727
+#define MSM_BUS_SLAVE_GNOC_SNOC 728
+#define MSM_BUS_SLAVE_QM_CFG 729
+#define MSM_BUS_SLAVE_TLMM_EAST 730
+#define MSM_BUS_SLAVE_TLMM_NORTH 731
+#define MSM_BUS_SLAVE_TLMM_WEST 732
+#define MSM_BUS_SLAVE_SKL 733
+#define MSM_BUS_SLAVE_LAST 734
#define MSM_BUS_SYSTEM_FPB_SLAVE_SYSTEM MSM_BUS_SYSTEM_SLAVE_SYSTEM_FPB
#define MSM_BUS_CPSS_FPB_SLAVE_SYSTEM MSM_BUS_SYSTEM_SLAVE_CPSS_FPB
#define ICBID_MASTER_XI_HSIC 141
#define ICBID_MASTER_SGMII 142
#define ICBID_MASTER_SPMI_FETCHER 143
+#define ICBID_MASTER_GNOC_BIMC 144
+#define ICBID_MASTER_CRVIRT_A2NOC 145
+#define ICBID_MASTER_CNOC_A2NOC 146
+#define ICBID_MASTER_WLAN 147
+#define ICBID_MASTER_MSS_CE 148
#define ICBID_SLAVE_EBI1 0
#define ICBID_SLAVE_APPSS_L2 1
#define ICBID_SLAVE_BIMC_PCNOC 202
#define ICBID_SLAVE_PCNOC_BIMC_1 203
#define ICBID_SLAVE_SPMI_FETCHER 204
+#define ICBID_SLAVE_MMSS_SMMU_CFG 205
+#define ICBID_SLAVE_WLAN 206
+#define ICBID_SLAVE_CRVIRT_A2NOC 207
+#define ICBID_SLAVE_CNOC_A2NOC 208
+#define ICBID_SLAVE_GLM 209
+#define ICBID_SLAVE_GNOC_BIMC 210
+#define ICBID_SLAVE_GNOC_SNOC 211
+#define ICBID_SLAVE_QM_CFG 212
+#define ICBID_SLAVE_TLMM_EAST 213
+#define ICBID_SLAVE_TLMM_NORTH 214
+#define ICBID_SLAVE_TLMM_WEST 215
#endif
--- /dev/null
+/* Copyright (c) 2015, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __QCOM_RPM_SMD_REGULATOR_H
+#define __QCOM_RPM_SMD_REGULATOR_H
+
+#define RPM_SMD_REGULATOR_LEVEL_NONE 0
+#define RPM_SMD_REGULATOR_LEVEL_RETENTION 16
+#define RPM_SMD_REGULATOR_LEVEL_RETENTION_PLUS 32
+#define RPM_SMD_REGULATOR_LEVEL_MIN_SVS 48
+#define RPM_SMD_REGULATOR_LEVEL_LOW_SVS 64
+#define RPM_SMD_REGULATOR_LEVEL_SVS 128
+#define RPM_SMD_REGULATOR_LEVEL_SVS_PLUS 192
+#define RPM_SMD_REGULATOR_LEVEL_NOM 256
+#define RPM_SMD_REGULATOR_LEVEL_NOM_PLUS 320
+#define RPM_SMD_REGULATOR_LEVEL_TURBO 384
+#define RPM_SMD_REGULATOR_LEVEL_BINNING 512
+
+#endif
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