all regression tests passed. but not displayed???

diff --git a/de0_cv_nes/mos6502.vhd b/de0_cv_nes/mos6502.vhd
index 9c302c5..0c17941 100644 (file)
--- a/de0_cv_nes/mos6502.vhd
+++ b/de0_cv_nes/mos6502.vhd
@@ -1341,7 +1341,7 @@ end;
                     ) then\r
                     reg_r_nw    <= '0';\r
                 else\r
-                    reg_r_nw    <= 'Z';\r
+                    reg_r_nw    <= '1';\r
                 end if;\r
 \r
                 --address bus out.\r
@@ -1437,7 +1437,7 @@ end;
                     ) then\r
                     reg_r_nw    <= '0';\r
                 else\r
-                    reg_r_nw    <= 'Z';\r
+                    reg_r_nw    <= '1';\r
                 end if;\r
 \r
                 --address bus out.\r
@@ -1477,7 +1477,7 @@ end;
                     ) then\r
                     reg_r_nw    <= '0';\r
                 else\r
-                    reg_r_nw    <= 'Z';\r
+                    reg_r_nw    <= '1';\r
                 end if;\r
                 if (reg_inst = conv_std_logic_vector(16#48#, 8)) then\r
                     --pha\r
@@ -1505,7 +1505,7 @@ end;
                     ) then\r
                     reg_r_nw    <= '0';\r
                 else\r
-                    reg_r_nw    <= 'Z';\r
+                    reg_r_nw    <= '1';\r
                 end if;\r
             elsif (reg_main_state = ST_A53_T4) then\r
                 --push pcl\r
@@ -1518,7 +1518,7 @@ end;
                     ) then\r
                     reg_r_nw    <= '0';\r
                 else\r
-                    reg_r_nw    <= 'Z';\r
+                    reg_r_nw    <= '1';\r
                 end if;\r
             elsif (reg_main_state = ST_A53_T5) then\r
                 if (reg_sub_state = ST_SUB00) then\r