[PowerPC] Tell VSX swap removal that scalar conversions are lane-sensitive

This is a rather non-controversial change. We were missing these instructions
from the list of instructions that are lane-sensitive. These two put the result
into lane 0 (BE) or 3 (LE) regardless of the input. This patch fixes PR36068.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324005 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/PowerPC/PPCVSXSwapRemoval.cpp b/lib/Target/PowerPC/PPCVSXSwapRemoval.cpp
index 8a5fb9f..3af2ab9 100644 (file)
--- a/lib/Target/PowerPC/PPCVSXSwapRemoval.cpp
+++ b/lib/Target/PowerPC/PPCVSXSwapRemoval.cpp
@@ -519,6 +519,8 @@ bool PPCVSXSwapRemoval::gatherVectorInstructions() {
       // permute control vectors (for shift values 1, 2, 3).  However,
       // VPERM has a more restrictive register class.
       case PPC::XXSLDWI:
+      case PPC::XSCVDPSPN:
+      case PPC::XSCVSPDPN:
         break;
       }
     }

diff --git a/test/CodeGen/PowerPC/pr36068.ll b/test/CodeGen/PowerPC/pr36068.ll
new file mode 100644 (file)
index 0000000..aac659b
--- /dev/null
+++ b/test/CodeGen/PowerPC/pr36068.ll
@@ -0,0 +1,18 @@
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-unknown < %s  | \
+; RUN:   FileCheck %s
+
+@glob = common local_unnamed_addr global <4 x float> zeroinitializer, align 4
+
+; Function Attrs: norecurse nounwind
+define void @test(float %a, <4 x float>* nocapture readonly %b) {
+; CHECK-LABEL: test
+; CHECK: xscvdpspn [[REG:[0-9]+]], 1
+; CHECK: xxspltw {{[0-9]+}}, [[REG]], 0
+entry:
+  %splat.splatinsert = insertelement <4 x float> undef, float %a, i32 0
+  %splat.splat = shufflevector <4 x float> %splat.splatinsert, <4 x float> undef, <4 x i32> zeroinitializer
+  %0 = load <4 x float>, <4 x float>* %b, align 4
+  %mul = fmul <4 x float> %splat.splat, %0
+  store <4 x float> %mul, <4 x float>* @glob, align 4
+  ret void
+}