drm/amdgpu: update golden setting programming logic

Since from soc15, make sure only AndMasked bit get changed
when applied or_mask

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Le Ma <Le.Ma@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index a70d0a4..16fd5da 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -509,7 +509,10 @@ void amdgpu_device_program_register_sequence(struct amdgpu_device *adev,
                } else {
                        tmp = RREG32(reg);
                        tmp &= ~and_mask;
-                       tmp |= or_mask;
+                       if (adev->family >= AMDGPU_FAMILY_AI)
+                               tmp |= (or_mask & and_mask);
+                       else
+                               tmp |= or_mask;
                }
                WREG32(reg, tmp);
        }

diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c
index 4eb615d..fa9c27d 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/soc15.c
+++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
@@ -378,7 +378,7 @@ void soc15_program_register_sequence(struct amdgpu_device *adev,
                } else {
                        tmp = RREG32(reg);
                        tmp &= ~(entry->and_mask);
-                       tmp |= entry->or_mask;
+                       tmp |= (entry->or_mask & entry->and_mask);
                }
 
                if (reg == SOC15_REG_OFFSET(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_3) ||