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Make XOP imply AVX as its needed to legalize the registers types.
author
Craig Topper
<craig.topper@gmail.com>
Tue, 1 May 2012 05:41:41 +0000
(
05:41
+0000)
committer
Craig Topper
<craig.topper@gmail.com>
Tue, 1 May 2012 05:41:41 +0000
(
05:41
+0000)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155891
91177308
-0d34-0410-b5e6-
96231b3b80d8
lib/Target/X86/X86.td
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diff --git
a/lib/Target/X86/X86.td
b/lib/Target/X86/X86.td
index
14b6b24
..
40c9667
100644
(file)
--- a/
lib/Target/X86/X86.td
+++ b/
lib/Target/X86/X86.td
@@
-96,7
+96,8
@@
def FeatureFMA4 : SubtargetFeature<"fma4", "HasFMA4", "true",
"Enable four-operand fused multiple-add",
[FeatureAVX]>;
def FeatureXOP : SubtargetFeature<"xop", "HasXOP", "true",
- "Enable XOP instructions">;
+ "Enable XOP instructions",
+ [FeatureAVX]>;
def FeatureVectorUAMem : SubtargetFeature<"vector-unaligned-mem",
"HasVectorUAMem", "true",
"Allow unaligned memory operands on vector/SIMD instructions">;